Edge-Addition Clock Delay Circuit for Femtosecond Sampling Precision
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Solution Overview
Problem
Existing clock delay adjusting circuits lack the precision required for high-speed, high-precision time-share sampling ADCs, with adjustment accuracy limited to the order of 10−12 seconds, which is insufficient for accurate clock delay adjustments.
Innovation Solution
A clock delay adjusting circuit based on edge addition, comprising a clock delay unit for equal-interval delays, a weight coefficient unit for generating weight signals, and an edge addition unit for weighted summation of clock signals to produce new clock signals with continuous rising or falling edges, allowing for precise adjustment of clock transmission path delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a clock delay adjusting circuit based on delay unit selection is used, then the circuit structure is simple, but the adjustment accuracy is limited to the order of 10^-12 seconds
Solution Approach 1:
The clock signal is segmented into multiple delay clock signals with equal time intervals through the clock delay unit. By selecting and combining different segments (delay clock signals) based on digital codes, the circuit achieves fine-grained delay adjustment. This segmentation allows the system to achieve 10^-15 second accuracy by combining multiple coarser delay units rather than requiring a single ultra-precise delay unit.
Solution Approach 2:
The invention transitions from selecting single delay units to combining multiple delay units with equal intervals through weighted summation. This adds a temporal dimension to the delay adjustment mechanism, where multiple delay clock signals at different time points are combined to achieve precise delay control. The edge addition unit creates continuous rising/falling edges by summing multiple delayed clock signals, enabling sub-delay-unit precision.
2Measurement precision
If multiple delay units are connected in sequence with selection circuit, then delay adjustment is achievable, but the adjustment precision is insufficient for high-speed time-share sampling ADC
Solution Approach 1:
The clock delay unit pre-generates multiple delay clock signals with equal time intervals before the selection and combination stage. This preliminary action ensures that all possible delay positions are prepared in advance, allowing the system to quickly select and combine the appropriate signals for the desired delay without real-time computation or complex feedback control during operation.
Solution Approach 2:
The edge addition unit acts as an intermediary that combines multiple delay clock signals through weighted summation to produce the final delayed clock signal. This intermediary component enables smooth transition and precise control by averaging or selectively combining multiple input signals, achieving higher precision than any single delay unit could provide while maintaining high-speed operation for time-share sampling ADC.
Data Source
AI summary
The invention provides a clock delay adjusting circuit based on edge addition and an integrated chip thereof. The clock delay adjusting circuit comprises a clock delay unit, a weight coefficient unit and an edge addition unit, wherein the clock delay unit is used for conducting equal-interval delay on clock signals inputted into the input end of the clock delay unit to obtain and output at least three delay clock signals at equal intervals, the weight coefficient unit is used for generating weight signals with the number the same as the number of the delay clock signals according to digital codes inputted into the input end of the weight coefficient unit and outputting the weight signals, and the edge addition unit is used for receiving the delay clock signals and the weight signals, conducting weighted summation on the delay clock signals according to the weight signals and outputting signals obtained through weighted summation to obtain new clock signals with continuous clock rising edges/continuous clock falling edges, wherein the number of the new clock signals is the same as the number of the delay clock signals. In addition, the clock delay adjusting circuit can be made into the integrated chip. In view of the present invention, the problems that an existing clock delay adjusting circuit is low in adjustment accuracy and can not meet the requirement for high-precision time-share sampling are well solved.