Edge Adhesive Pattern for Semiconductor Package Stress Reduction
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high-density chip stacking with package-on-package (POP) technology due to lower yield rates and increased defect rates in end products, particularly in miniaturized electronic devices, where the thermal expansion coefficients of different semiconductor chips can cause stress and contact failures in interconnect terminals.
Innovation Solution
A semiconductor package design featuring a lower package with a semiconductor chip, an upper package stacked on it, interconnect terminals, and an adhesive pattern that extends along the edge of the chip to expose the central zone, minimizing the adhesive material used while effectively fastening the packages together and reducing stress on interconnect terminals, using materials like Non-Conductive Paste or Anisotropic Film to manage thermal expansion differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If adhesive material is applied extensively to fasten packages together, then bonding strength is improved, but stress on interconnect terminals increases due to thermal expansion differences
Solution Approach 1:
The adhesive pattern is applied selectively at specific locations (edges and corners of the semiconductor chip) rather than covering the entire surface. This localized application provides sufficient bonding strength while minimizing the adhesive's restraining effect on thermal expansion, thereby reducing stress on interconnect terminals and improving their reliability.
Solution Approach 2:
The adhesive application is segmented into discrete locations (edges and corners) rather than continuous coverage. This segmentation allows different regions of the package to expand and contract independently during thermal cycling, reducing overall stress on the interconnect terminals while maintaining adequate bonding strength at the segmented adhesive locations.
2Reliability
If adhesive material is minimized to reduce stress, then interconnect terminal reliability is improved, but bonding strength between packages decreases
Solution Approach 1:
The adhesive is concentrated at strategic locations (edges and corners) where it provides maximum bonding effectiveness. This localized quality approach ensures sufficient bonding strength is achieved with minimal adhesive material, allowing the central chip area to remain free of adhesive and reducing overall stress on interconnect terminals.
Solution Approach 2:
Instead of applying adhesive uniformly across the entire chip surface (excessive action), the adhesive is applied partially only at the edges and corners. This partial action is sufficient to provide the necessary bonding strength between packages while minimizing the total adhesive volume that would otherwise create thermal expansion stress.
3Quantity of substance
If adhesive pattern covers entire chip surface, then bonding coverage is improved, but manufacturing precision is reduced due to misalignment and defect risks
Solution Approach 1:
The adhesive pattern is localized to specific geometric features (edges and corners of the chip) that are easy to identify and align during manufacturing. This localized approach improves manufacturing precision by providing clear alignment references while reducing the total adhesive coverage area, thereby minimizing misalignment risks and manufacturing defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability of semiconductor packages by reducing stress on interconnect terminals, minimizing adhesive material usage, and preventing contact failures, thereby improving the yield and functionality of miniaturized electronic devices.
Implementation Method 1
an adhesive pattern between a top surface of the semiconductor chip and a bottom surface of the second substrate. The adhesive pattern may extend along an edge of the semiconductor chip.
Implementation Method 2
the thermal expansion coefficients of different semiconductor chips can cause stress and contact failures in interconnect terminals
Data Source
AI summary
A semiconductor package is disclosed. The semiconductor package comprises a lower package including a first substrate and a semiconductor chip on the first substrate, a second substrate on the lower package, interconnect terminals between the first substrate and the second substrate, and an adhesive pattern between a top surface of the semiconductor chip and a bottom surface of the second substrate. The adhesive pattern extends along an edge of the semiconductor chip. The adhesive pattern exposes a top surface of a central zone of the semiconductor chip.