Edge-Aligned Voltage Level Shifting for Lower Timing Degradation
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Solution Overview
Problem
Voltage level shifters currently experience significant timing degradation and occupy substantial IC footprint due to the large number of devices required, leading to unreliable signal processing and increased delay in voltage level shifting operations.
Innovation Solution
The use of edge alignment circuits, which include a first field effect transistor (FET) and an inverter coupled in series between voltage rails, effectively aligns the timing of signals across different voltage domains, reducing timing degradation and minimizing the number of devices required, thereby reducing IC footprint and delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional voltage level shifters use multiple devices to achieve voltage domain conversion, then voltage level shifting functionality is achieved, but timing degradation increases and IC footprint increases
Solution Approach 1:
The patent applies preliminary action by pre-aligning the timing edges of signals from different voltage domains before they are processed by the voltage level shifter. Edge alignment circuits generate aligned versions of input signals in advance, ensuring that when signals reach the voltage level shifter, their timing is already synchronized. This eliminates the need for complex timing compensation circuits and reduces overall timing degradation in the signal processing path.
Solution Approach 2:
The patent introduces edge alignment circuits as intermediary components between the input signals and the voltage level shifter. These intermediary circuits generate aligned signal versions that serve as mediators, facilitating proper timing synchronization without requiring the main voltage level shifter to handle timing correction. This intermediary approach separates the timing alignment function from the voltage conversion function, allowing each to be optimized independently.
2Reliability
If traditional voltage level shifters use multiple devices to ensure reliable signal processing, then signal processing reliability is improved, but device quantity and IC footprint increase
Solution Approach 1:
The patent segments the voltage level shifter into multiple independent functional blocks, each handling specific voltage domain conversions. By dividing the overall voltage conversion task into smaller segments operating in parallel or sequence, the system achieves reliable signal processing through modular redundancy while using fewer total devices compared to a single monolithic voltage level shifter. Each segment can be independently optimized and tested.
Solution Approach 2:
The patent performs preliminary signal alignment and conditioning before the main voltage conversion process. Edge alignment circuits prepare signals in advance by pre-synchronizing their timing characteristics, which eliminates the need for additional timing compensation devices in the main signal path. This preliminary preparation reduces the overall device count while maintaining signal processing reliability.
3Adaptability or versatility
If voltage level shifters process signals from different voltage domains, then multi-voltage domain operation is achieved, but timing degradation and processing delay increase
Solution Approach 1:
The patent applies preliminary action by pre-aligning the timing edges of signals from different voltage domains before they are processed by the voltage level shifter. Edge alignment circuits generate aligned versions of input signals in advance, ensuring that when signals reach the voltage level shifter, their timing is already synchronized. This eliminates the need for complex timing compensation circuits and reduces overall timing degradation in the signal processing path.
Solution Approach 2:
The patent implements a universal voltage level shifter design that can handle multiple voltage domain conversions through a single integrated structure. The voltage level shifter is designed to accept inputs from various voltage domains and produce outputs in target voltage domains using a unified conversion mechanism. This multi-functional approach reduces processing delay compared to having separate dedicated converters for each voltage domain pair.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The edge alignment circuits significantly reduce timing degradation and delay, ensuring accurate signal processing across different voltage domains while occupying a smaller IC footprint compared to traditional voltage level shifters.
Implementation Method 1
a first field effect transistor (FET) including a first gate configured to receive a first input signal that varies in accordance with a first voltage domain
Data Source
AI summary
An aspect of the disclosure relates to an apparatus including a first field effect transistor (FET) including a first gate configured to receive a first input signal that varies in accordance with a first voltage domain; and a first inverter including a first input configured to receive a second input signal that varies in accordance with a second voltage domain, and a first output configured to generate a first output signal that varies in accordance with the second voltage domain, wherein the first output signal is based on the first and second input signals, and wherein the first FET and the first inverter are coupled in series between first and second voltage rails. Per another aspect, the apparatus includes additional circuitry to allow the apparatus to process signals in accordance with a third voltage domain.