Edge-Based Data Encoding for 4-Wire Bus Clock Recovery
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Solution Overview
Problem
Existing data transmission interfaces over 4-wire data buses are limited by the need for a dedicated clock wire, which restricts data rate and increases electromagnetic interference and licensing costs, especially when using high-speed I/O interfaces like Ethernet or CSI-2.
Innovation Solution
A data encoding scheme that uses all four wires for data transmission without a dedicated clock wire, employing a lookup table and shift registers to generate time-dependent binary signals with edges, allowing full clock recovery at the receiver and enabling higher data rates while reducing electromagnetic interference and licensing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated clock wire is used for data transmission, then clock synchronization is improved, but the data rate is limited and electromagnetic interference increases
Solution Approach 1:
The patent merges the clock signal and data signals into the same four-wire bus by encoding data using signal edges (rising/falling edges) on the data wires themselves. The receiver detects these edges to recover both clock timing and data information, eliminating the need for a separate clock wire while maintaining synchronization and maximizing data rate.
Solution Approach 2:
The data wires are given multi-functionality by serving both as data transmission carriers and as clock signal carriers through edge-based encoding. Each data wire can convey data bits while its edges provide timing information, allowing all four wires to participate in data transmission simultaneously.
2Device complexity
If a dedicated clock wire is used, then clock recovery is simplified, but electromagnetic interference and licensing costs increase
Solution Approach 1:
The clock signal is combined with data signals on the same wires through edge-based encoding. The receiver recovers clock timing by detecting signal edges on the data wires, eliminating the need for a separate clock wire and reducing electromagnetic interference while keeping clock recovery manageable through edge detection circuits.
3Device complexity
If standard GPIO pins are used without dedicated HSIO interface, then licensing costs and hardware complexity are reduced, but data transmission capability is limited
Solution Approach 1:
The patent changes the encoding parameter from traditional voltage-level logic to edge-based encoding, where data is represented by rising and falling edges on the signal wires. This allows standard GPIO pins to achieve high-speed data transmission capability comparable to dedicated HSIO interfaces, eliminating the need for expensive licensed hardware while maintaining high productivity.
Data Source
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AI summary
The disclosure relates to a data transmission interface (108) for use in a first integrated circuit (102), IC, for encoding and sending a data packet (100) from the first IC to a second IC (104) via a data bus (106) having four data wires (W1...W4), the data transmission interface arranged to generate four time-dependent binary signals (V1...V4) which jointly encode the data packet in signal edges (112) thereof, each of the signals being associated with a unique wire of the data bus and spanning a temporal cycle T within which are defined four consecutive time stamps T1...T4 at which edges can occur in the signals, the data transmission interface further arranged to transmit the signals to the second IC substantially in parallel on their respective data wires, wherein: irrespective of the data packet content, at each time stamp T1...T4 at least one of the four signals has an edge to enable clock recovery at the second IC; the time difference between T2 and T3 is greater than both the time difference between T1 and T2 and also the time difference between T3 and T4; and no signal has edges at both T1 and T2 and no signal has edges at both T3 and T4.