Semiconductor Package Pad Openings for Edge Bump Delamination
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Solution Overview
Problem
Copper pillar bumps in semiconductor packages experience stress due to differing thermal expansion coefficients between copper and dielectric materials, leading to potential delamination and integrity issues in interconnects during heating-cooling cycles, especially at discrete regions without coverage from dielectric layers.
Innovation Solution
A semiconductor package design featuring at least two discrete regions of a conductive pad exposed and free from dielectric coverage, which helps in reducing stress concentration and balancing thermal stress, with an under bump metallurgy layer and strategically positioned conductive bumps to counteract warping substrate stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If copper pillar bumps are used to achieve finer pitches and reduce capacitance load, then productivity and performance are improved, but stress-induced delamination occurs during heating-cooling cycles due to differing thermal expansion coefficients
Solution Approach 1:
The patent applies local quality by creating discrete exposed regions of the conductive pad where the dielectric layer is intentionally removed. These localized exposed regions are positioned around the copper pillar bump to specifically address stress concentration at the bump-dielectric interface, while the rest of the dielectric layer remains intact to provide overall protection and insulation.
Solution Approach 2:
The dielectric layer is segmented by creating discrete openings or exposed regions rather than removing the entire layer. This segmentation allows the structure to accommodate thermal expansion differences at specific locations while maintaining the integrity and protective function of the dielectric layer in other areas.
2Reliability
If discrete regions of conductive pad are exposed from dielectric layer to reduce stress concentration, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
Instead of completely removing the dielectric layer or creating complex patterns, the patent uses partial action by creating discrete, localized exposed regions. This partial removal is sufficient to address the stress concentration problem at the copper pillar bump interface without requiring extensive dielectric layer modification throughout the entire structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively mitigates stress-induced delamination and enhances the integrity of interconnects by distributing thermal stress across multiple discrete regions, improving the reliability and performance of semiconductor packages.
Implementation Method 1
Copper pillar bumps in semiconductor packages experience stress due to differing thermal expansion coefficients between copper and dielectric materials
Data Source
AI summary
The present disclosure provides a semiconductor package including a semiconductor chip and a package substrate. The semiconductor chip includes a substrate, a plurality of conductive pads in the substrate, and a plurality of conductive bumps. Each of the conductive bumps is over corresponding conductive pad. At least one of the conductive bumps proximity to an edge of the semiconductor chip is in contact with at least two discrete regions of the corresponding conductive pad. The package substrate has a concave surface facing the semiconductor chip and joining the semiconductor chip through the plurality of conductive bumps.