Edge Clock Model for Digital Circuit Formal Verification
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Solution Overview
Problem
Current digital circuit design verification methods face challenges in accurately modeling and managing clock specifications, leading to inaccuracies and complexities in capturing and analyzing states, especially in large and complex circuits.
Innovation Solution
The use of an edge clock model to capture states at clock edges based on a clock specification, allowing for more precise and efficient formal verification, which can also generate states for other clock models like the phase clock model, reducing inaccuracies and simplifying state management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If highly detailed simulation and modeling is used to model clock specifications, then measurement precision of clock timing is improved, but device complexity and difficulty of detecting and measuring increase
Solution Approach 1:
The patent extracts only the essential clock edge transition information from complex clock specifications, separating the critical timing events from unnecessary detailed modeling. This allows formal verification to focus on state capture at meaningful clock edges without being overwhelmed by complete clock waveform modeling.
Solution Approach 2:
The patent segments the clock specification into discrete clock edges or transitions, treating each edge as an independent event for state capture. This segmentation reduces the continuous complex clock signal into manageable discrete events that can be systematically processed during verification.
2Reliability
If exhaustive mathematical and analytical techniques are used for formal verification, then reliability of error detection is improved, but loss of time increases
Solution Approach 1:
The patent performs preliminary state capture at clock edges before formal verification begins. By pre-identifying and capturing states at meaningful clock transitions, the verification process can start from these prepared states rather than requiring exhaustive analysis from all possible initial states, thus reducing verification time while maintaining reliability.
3Measurement precision
If states are captured at all times for comprehensive analysis, then measurement precision of state information is improved, but device complexity and loss of time increase
Solution Approach 1:
The patent captures states periodically at clock edges rather than continuously. This periodic sampling at meaningful time intervals (clock transitions) provides sufficient state information for verification while dramatically reducing the computational overhead and time required compared to continuous state monitoring and management.
Data Source
AI summary
An edge clock model is used to capture states from a logic-level simulation of a circuit description. The states are captured at clock edges, or transitions, according to an edge clock model based on a clock specification for the circuit description. The captured states and associated attributes are used in formal verification of the circuit description. This approach helps to reduce or eliminate inaccuracies and other issues with other clock models such as a phase clock model. In one embodiment, a phase clock model can be used in addition to the edge clock model. In another embodiment, the edge clock states can be used to generate states according to different clock models, such as the phase clock model.