Edge Combiner Delay Path for Symmetrical High-Speed Timing

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Solution Overview

Problem

Conventional edge combiners in timing systems often have unsymmetrical operation ranges at high speeds, leading to malfunctions in noisy environments like laser diode drivers, where one side of the operation range is narrower than the other, and reducing pulse width to address this issue risks circuit malfunctions.

Innovation Solution

An edge combiner design that includes a circuit state element, a pulse generator, a first delay circuit, and an output logic gate with signal paths that bypass and include the delay circuit, ensuring symmetrical operation range by maintaining equal output pulse width to the input phase difference between timing signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional edge combiners are used at high speeds, then operation speed is improved, but operation range symmetry deteriorates

Engineering Contradiction:
Improveoperation speedVSAvoidoperation range symmetry
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies asymmetry principle by intentionally introducing a delay circuit in one signal path (but not the other) to compensate for inherent circuit asymmetries. The delay circuit creates a controlled asymmetric delay that balances the overall operation range, allowing the edge combiner to achieve symmetrical performance at high speeds despite the asymmetric circuit structure.

Inventive Principle:
Principle #4Asymmetry

2Adaptability or versatility

If pulse width is reduced to expand operation range, then operation range is improved, but circuit reliability deteriorates

Engineering Contradiction:
Improveoperation rangeVSAvoidcircuit reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies parameter changes by adjusting the delay amount in the delay circuit to optimize the operation range. By carefully selecting the delay parameter, the circuit achieves expanded operation range while maintaining sufficient pulse widths for reliable operation, avoiding the reliability issues that would result from excessive pulse width reduction.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If delay circuit is added to achieve symmetrical operation, then operation range symmetry is improved, but device complexity increases

Engineering Contradiction:
Improveoperation range symmetryVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies the intermediary principle by introducing a delay circuit as a mediator element between the timing signals and the output logic. This intermediary component simplifies the overall design by providing a straightforward mechanism to achieve symmetry, rather than requiring complex calibration circuits or multiple adjustment elements.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20230107400A1Edge combiners with symmetrical operation range at high speed
Publication Date: 2023.04.06 ANALOG DEVICES INT UNLTD CO
  • US20230107400A1 patent drawing
  • US20230107400A1 patent drawing
  • US20230107400A1 patent drawing

AI summary

Edge combiners with symmetrical operation range at high speed are provided. In certain embodiments, an edge combiner (80) includes a circuit state element (71) having a first input controlled by a first timing signal (SI), and a pulse generator (72) that resets the circuit state element by controlling a second input (R) of the circuit state element based on a second timing signal (S2). The edge combiner further includes a first delay circuit (75), and an output logic gate (77) having a first input connected to a data output (Q) of the circuit state element through a first signal path that bypasses the first delay circuit (75), a second input (QD) connected to the data output through a second signal path that includes the first delay circuit, and an output (OUT) that provides an output signal indicating delay between an edge of the first timing signal and an edge of the second timing signal.