Edge Compression Layers for Semiconductor Crack Mitigation
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Solution Overview
Problem
The dicing process in semiconductor device fabrication induces stress that can lead to crack formation and propagation into the active circuit area of chips, causing failures and reducing the yield of functional chips.
Innovation Solution
A chip structure is designed with a crackstop extending through the interconnect structure, featuring a groove extending from the crackstop to the substrate, and a stress-containing layer applied to the groove to mitigate crack initiation and propagation, using materials like titanium nitride with compressive stress to reduce the likelihood of cracks and delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the dicing process is used to singulate chips from the wafer, then chip production is achieved, but stress cracks are induced that can propagate into the active circuit area causing chip failures
Solution Approach 1:
The interconnect structure is segmented into multiple levels with crackstops positioned at specific locations to interrupt crack propagation paths. The groove structure divides the continuous interconnect structure into sections, preventing cracks from traveling across the entire chip while maintaining electrical functionality through the crackstop designs.
Solution Approach 2:
Crackstops and grooves are formed in the interconnect structure before the dicing process occurs. This preliminary structuring of the interconnect layers creates predetermined paths that deflect or stop cracks before they can reach the active circuit area during subsequent dicing operations.
2Reliability
If crackstops are added to the interconnect structure to prevent crack propagation, then chip reliability is improved, but device complexity increases
Solution Approach 1:
Crackstops are implemented only at specific strategic locations within the interconnect structure where crack propagation is most likely to occur, rather than throughout the entire structure. This localized approach provides crack protection while minimizing the addition of structural complexity and maintaining manufacturing efficiency.
3Reliability
If a stress-containing layer is applied to the groove to reduce crack initiation, then chip reliability is enhanced, but manufacturing complexity increases
Solution Approach 1:
The stress-containing layer modifies the mechanical stress parameters in the interconnect structure by introducing compressive stress through materials like titanium nitride. This parameter change in the stress state prevents crack initiation at the groove locations during dicing, enhancing reliability while using standard deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress-containing layer effectively reduces the probability of crack initiation and propagation, enhancing chip reliability and yield by neutralizing pre-existing cracks and pinning the interconnect structure edges, thereby reducing the need for additional crackstops and minimizing delamination.
Implementation Method 1
a stress-containing layer applied to the groove to mitigate crack initiation and propagation, using materials like titanium nitride with compressive stress
Data Source
AI summary
Structures for a chip, as well as methods of fabricating such chip structures. The chip including a portion of a substrate, an active circuit region associated with the portion of the substrate, an interconnect structure on the active circuit region, and a crackstop extending through the interconnect structure. A groove extends through the interconnect structure to the substrate at a location exterior of the crackstop. A stress-containing layer is formed on at least a portion of the groove.