Edge Compute Components Under Memory Array
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Solution Overview
Problem
Existing memory devices face limitations in implementing compute components under memory arrays due to size and control access constraints, which restrict their operational capabilities and efficiency.
Innovation Solution
Implementing compute components directly under or near the edge of the memory array, rather than in its interior, allows for greater control access and reduced data processing, enabling a wider range of operations and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If compute components are implemented in the interior of the memory array, then manufacturing density is improved, but control access and operational flexibility deteriorate
Solution Approach 1:
The patent transitions from a two-dimensional planar integration approach to a three-dimensional vertical stacking architecture. Compute components are positioned in the vertical dimension beneath the memory array, allowing simultaneous achievement of high density (through vertical stacking) and good accessibility (through edge positioning that maintains lateral access paths). This dimensional transition resolves the contradiction by decoupling density from lateral footprint constraints.
Solution Approach 2:
The patent implements a nested vertical stacking structure where compute components are embedded beneath the memory array in a tiered configuration. The memory array sits on top of the compute components, creating a nested arrangement that maximizes space utilization while maintaining access paths. This nesting allows the system to achieve high manufacturing density without sacrificing control access capabilities.
2Area of stationary object
If compute components are implemented directly under the memory array, then area utilization is improved, but data processing requirements and complexity increase
Solution Approach 1:
The patent applies local quality by implementing compute components selectively at the edges of the memory array rather than uniformly across the entire area. This localized placement optimizes area utilization in regions where compute functionality provides maximum benefit while minimizing unnecessary complexity in regions where simple storage suffices. The edge positioning creates local zones of enhanced functionality without globally increasing system complexity.
Solution Approach 2:
The patent segments the memory array into distinct regions: edge regions with compute components and interior regions with pure storage. This segmentation allows different functional characteristics in different areas, enabling the system to achieve good area utilization through selective compute placement while reducing overall data processing requirements by limiting compute functionality to only where necessary.
3Ease of operation
If compute components are positioned at the edge of the memory array, then control access is improved, but manufacturing density decreases
Solution Approach 1:
The patent resolves this contradiction by moving the density optimization from the lateral (2D) dimension to the vertical (3D) dimension. Edge positioning maintains excellent control access in the lateral plane, while vertical stacking beneath the memory array compensates for the reduced lateral footprint by utilizing the third dimension for additional compute component placement, thereby achieving high manufacturing density without compromising access.
Solution Approach 2:
The patent employs dynamic resource allocation where compute components at the edge can dynamically access and process data from multiple memory locations. This dynamic accessibility means that even though edge positioning reduces lateral density, the compute components can efficiently service a larger portion of the memory array through intelligent data routing and processing, effectively compensating for the physical positioning trade-off.
Data Source
AI summary
Apparatuses and methods can be related to implementing edge compute components in a memory array. Compute components can be implemented under a memory array. Implementing compute components under a memory array can limit control access to the compute components due to die space utilized by the compute components. A portion of the compute components (e.g., compute components on the edge) may have control access that is not available to the remainder of the compute components.