Split-Path Equalization for High-Rate Clock Recovery Accuracy
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Solution Overview
Problem
Current clock and data recovery techniques face challenges in accurately recovering timing information at high signaling rates, as existing equalization methods are not effectively helpful for clock recovery and often result in higher bit-error rates and increased jitter.
Innovation Solution
A split-path equalizer is introduced, which applies independent equalization parameters to data and edge-sampling paths, using continuous-time linear equalizers and decision feedback equalization techniques to optimize signal recovery and minimize intersymbol interference, thereby enhancing clock recovery accuracy and reducing bit-error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional equalization methods are used for clock recovery at high signaling rates, then signal processing is simplified, but clock recovery accuracy deteriorates and bit-error rates increase
Solution Approach 1:
The equalization process is segmented into two independent paths: a data sampling path and an edge sampling path. Each path has its own equalizer with independently optimized parameters. The data sampling equalizer optimizes for data recovery while the edge sampling equalizer optimizes for clock recovery, allowing both functions to achieve high accuracy without interfering with each other.
Solution Approach 2:
Different equalization parameters are applied to different sampling paths based on their specific requirements. The data sampling path uses parameters optimized for minimizing bit-error rates in data recovery, while the edge sampling path uses parameters optimized for minimizing jitter in clock recovery. This local optimization allows each path to achieve its best possible performance.
2Device complexity
If conventional equalization methods are used for clock recovery at high signaling rates, then device structure is simplified, but jitter increases and clock recovery accuracy deteriorates
Solution Approach 1:
The equalizer is segmented into two independent equalization circuits, each dedicated to a specific sampling path. The first equalization circuit processes the data sampling path while the second equalization circuit processes the edge sampling path. This segmentation allows independent optimization of jitter performance in the edge sampling path without compromising data recovery performance.
Solution Approach 2:
The equalization parameters are changed and independently optimized for each sampling path. The edge sampling equalizer uses parameters specifically tuned to minimize jitter and improve clock recovery stability, while the data sampling equalizer uses parameters optimized for data accuracy. This parameter differentiation resolves the contradiction between structural simplicity and stability.
3Device complexity
If single equalization settings are used for both data and edge sampling, then device complexity is reduced, but both data recovery and clock recovery performance deteriorate
Solution Approach 1:
The equalization function is segmented into two independent circuits, each dedicated to one sampling path. This allows the system to maintain low complexity through modular design while achieving high reliability through path-specific optimization. Each equalizer can be independently tuned to minimize bit-error rates for its specific function.
Solution Approach 2:
Each equalization path is optimized with local quality principles, where the data sampling equalizer uses parameters optimized for data accuracy and the edge sampling equalizer uses parameters optimized for clock accuracy. This local optimization ensures both data recovery and clock recovery achieve high reliability simultaneously.
4Ease of manufacture
If conventional equalization is used, then implementation is simplified, but intersymbol interference increases and signal recovery accuracy deteriorates
Solution Approach 1:
The implementation is segmented into two independent equalization circuits that can be designed and manufactured separately. Each circuit handles a specific sampling path, making the overall implementation as simple as two identical circuits with different parameter settings, while achieving superior signal recovery accuracy through independent optimization.
Data Source
AI summary
This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.