Edge Detector Circuit for Jitter Reduction in Semiconductor ICs
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) experience increased integration rates, errors such as jitter and duty cycle changes in clock signals become more prevalent, leading to inaccuracies in signal delivery and analysis.
Innovation Solution
An edge detector system comprising a differential signal generator, a sense amplifier, and a latch is employed, which delays and inverts input signals to generate differential signals, amplifies differences, and resets signals at specific clock edges, maintaining the duty cycle and jitter of the input signal in the edge signal, thereby reducing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the integration rate of semiconductor IC increases, then the number of devices per unit area increases, but signal delivery errors such as jitter and duty cycle changes increase
Solution Approach 1:
The patent segments the signal analysis function into two parts: an edge detector circuit that generates edge signals for timing information, and a separate analysis unit that processes these signals. This segmentation allows accurate edge detection to be maintained while the analysis can be performed independently, resolving the contradiction between high integration rate and signal delivery accuracy.
Solution Approach 2:
The patent introduces an intermediary edge detector circuit that converts the complex clock signal into simplified edge signals. This intermediary component isolates the timing extraction function from the main signal path, allowing accurate edge detection without affecting the overall system integration and signal integrity.
2Speed
If a high frequency clock signal is used for signal analysis, then analysis speed improves, but power consumption increases
Solution Approach 1:
The patent uses periodic sampling of the clock signal at its rising and falling edges to generate edge signals. This periodic action allows the system to capture timing information at critical moments without continuously processing the entire high-frequency signal, thereby reducing power consumption while maintaining analysis speed.
Solution Approach 2:
The patent extracts only the essential timing information (edge transitions) from the high-frequency clock signal using the edge detector circuit. By taking out only the necessary timing data rather than processing the entire high-frequency signal, the system achieves fast analysis with reduced power consumption.
Data Source
AI summary
An edge detector includes a differential signal generator, a sense amplifier and a latch. The differential signal generator delays an input signal to generate a first differential signal and inverts the input signal to generate a second differential signal. The sense amplifier amplifies a difference between the first differential signal and the second differential signal to generate a first amplification signal and a second amplification signal at a first edge of a test clock signal and resets the first amplification signal and the second amplification signal at a second edge of the test clock signal. The latch generates an edge signal corresponding to edge information of the input signal in response to the first amplification signal and the second amplification signal.