Edge Fin Thermal Force Balancing in Semiconductor Structures

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Solution Overview

Problem

Conventional FinFET semiconductor devices face performance inconsistencies due to deformation of edge fins during isolation material layer formation, leading to poor device performance and reduced integration density.

Innovation Solution

A method involving the formation of a first barrier layer on the sidewalls of edge fins to balance thermal forces, followed by a second barrier layer to prevent deformation, allowing for consistent semiconductor device performance and improved integration density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If isolation material layer is formed over the base substrate without barrier layer protection, then the isolation material layer can be deposited, but the edge fin deforms due to unbalanced thermal forces

Engineering Contradiction:
Improveedge fin shape consistencyVSAvoiddevice performance consistency
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A first barrier layer is formed on the sidewalls of the edge fin before the isolation material layer deposition. This preliminary protective layer balances thermal forces during subsequent processing steps, preventing edge fin deformation and ensuring consistent device performance across the semiconductor structure.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The first barrier layer acts as an intermediary between the edge fin and the isolation material layer. It mediates the thermal stress during deposition and processing, protecting the edge fin from direct thermal exposure that would cause deformation, while still allowing the isolation material layer to be formed over the structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If conventional FinFET fabrication is used, then manufacturing process is simple, but device performance is poor and integration density is reduced

Engineering Contradiction:
Improvedevice performanceVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The first and second barrier layers are formed in advance on the edge fin sidewalls before isolation material deposition. This preliminary protection enables subsequent processing steps to proceed without edge fin deformation, improving device performance while adding only moderate process complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention introduces additional material layers (barrier layers) with specific material properties that change the thermal and mechanical parameters of the edge fin structure. These parameter changes prevent deformation during processing, enabling high-performance devices while managing fabrication complexity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively prevents edge fin deformation and enhances the consistency of semiconductor device performance by balancing thermal forces during isolation material layer formation, thereby improving the integration density and performance of FinFET devices.

Implementation Method 1

forming a first barrier layer on sidewalls of the edge fin... effectively prevents edge fin deformation and enhances the consistency of semiconductor device performance by balancing thermal forces during isolation material layer formation

Methodology Applied
Scientific EffectThermal force balancing: Thermal Expansion

Data Source

PatentUS11562930B2Semiconductor structure
Publication Date: 2023.01.24 SEMICON MFG INT (SHANGHAI) CORP
  • US11562930B2 patent drawing
  • US11562930B2 patent drawing
  • US11562930B2 patent drawing

AI summary

A semiconductor structure is provided. The semiconductor structure includes a base substrate including a plurality of non-device regions; a middle fin structure and an edge fin disposed around the middle fin structure on the base substrate between adjacent non-device regions; a first barrier layer on sidewalls of the edge fin; and an isolation layer on the base substrate. The isolation layer has a top surface lower than the edge fin and the middle fin structure, and covers a portion of the sidewalls of each of the edge fin and the middle fin structure. The isolation layer further has a material density smaller than the first barrier layer.