Edge Fin Trimming for Uniform FinFET Widths
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Solution Overview
Problem
Existing fin formation processes for multi-gate devices like FinFETs result in uneven fin widths due to etch loading effects, leading to variations in device performance and process control.
Innovation Solution
The method involves forming semiconductor fins and then selectively removing or trimming the outer fins to achieve uniform fin widths, thereby reducing the etch loading effect and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor fins are formed in parallel groups using conventional etching, then fin formation efficiency is improved, but etch loading effects cause non-uniform fin widths with edge fins being wider than center fins
Solution Approach 1:
The fin structure is segmented into center fins and edge fins, with different etching processes applied to each segment. The mask pattern is divided into center mask portions and edge mask portions that are etched at different rates, allowing independent control of fin widths in different regions to achieve overall uniformity
Solution Approach 2:
Different etching conditions are applied locally to different regions of the substrate. The center mask portions receive different etching parameters than the edge mask portions, creating locally optimized fin widths that compensate for the etch loading effect and result in uniform fin widths across the entire array
2Ease of manufacture
If edge fins are wider than center fins due to etch loading, then fewer fins can be formed in edge regions, but this reduces the overall device performance and increases variability
Solution Approach 1:
The mask layer is preliminarily patterned with different thicknesses or compositions in center and edge regions before etching. This preliminary differentiation in mask properties compensates for the anticipated etch loading effects, ensuring that after etching, all fins achieve uniform widths and consistent device performance
Data Source
AI summary
Semiconductor structures and methods are provided. In one embodiment, a method of the present disclosure includes forming a plurality of semiconductor fins over a substrate, after the forming of the plurality of semiconductor fins, removing an outer semiconductor fin of the plurality of semiconductor fins, and forming a gate structure over the plurality of semiconductor fins. The plurality of semiconductor fins include more than 3 semiconductor fins and the removing recesses a portion of the substrate directly under the outer semiconductor fin.