Edge-Triggered Flip-Flop Layout for Low Clock Power at Low Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional Flip-flop designs for integrated circuits consume high clock power, leading to increased overall block power and area, and degrade performance, necessitating a solution for low power consumption with minimal impact on cell area and frequency.
Innovation Solution
A low voltage tolerant ultra-low power edge-triggered master-slave Flip-flop design is implemented, utilizing a p-type metal oxide semiconductor (PMOS) dominant master latch and an n-type metal oxide semiconductor (NMOS) dominant slave latch, with a clock signal and data signal processing mechanism that generates internal signals and output signals efficiently, optimizing clock power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional stacking technique is used to reduce power consumption, then power consumption is reduced, but Flip-flop performance degrades which impacts block frequency and increases total area
Solution Approach 1:
The Flip-flop is segmented into master and slave latches with distinct PMOS and NMOS dominance respectively, allowing independent optimization of each stage's power characteristics while maintaining overall performance
Solution Approach 2:
Different regions of the circuit (master latch vs slave latch) are given different transistor type dominances (PMOS vs NMOS) to optimize local power consumption characteristics without compromising global frequency performance
2Reliability
If conventional Flip-flop design with cross-coupled inverters is used, then data storage function is achieved, but clock power consumption is high
Solution Approach 1:
The circuit parameters are changed by introducing PMOS dominant and NMOS dominant latch structures with specific transistor sizing ratios, optimizing the power consumption while maintaining data storage reliability
Solution Approach 2:
The circuit uses dynamic clock gating mechanisms where pass gates are controlled by clock signals to enable data transfer only during required periods, reducing unnecessary clock power consumption
3Reliability
If robust Jam latch is used in master latch, then reliability is improved, but power consumption increases
Solution Approach 1:
The problematic Jam latch structure is extracted and replaced with a simplified PMOS dominant latch structure that achieves reliability through different means (transistor sizing and configuration) rather than complex feedback mechanisms
Solution Approach 2:
The design uses simpler latch structures that can be rapidly switched and reset, accepting short-lived state transitions in exchange for lower power consumption compared to robust but power-hungry Jam latches
Data Source
AI summary
A method and a flip-flop for designing low power integrated circuits (IC's). The method includes receiving at least one of a clock signal, a data signal, and a complimentary data signal. The complimentary data signal is produced by an input data inverter present in the flip-flop. Further, the method includes generating at least one master internal signal based on the received at least one of the clock signal, the data signal, and the complimentary data signal, when the clock signal is at a low logic level. Further, the method includes generating at least one slave internal signal based on at least one of the received clock signal and the generated at least one master internal signal, when the clock signal is at a high logic level. Further, the method includes generating an output signal based on the generated at least one slave internal signal.