Edge Interconnect Semiconductor Packages Without Interposers
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Solution Overview
Problem
As integration density increases in semiconductor packages, connecting integrated circuit dies through interposers alone becomes challenging due to the limitations in interposer-based interconnects, which restricts further integration and performance enhancement.
Innovation Solution
The implementation of edge interconnect features on integrated circuit dies, which are conductive lines extending through sealing rings and exposed on edge surfaces, allowing direct connection between dies without interposers, utilizing an inter-chip redistribution layer (RDL) formed by patterning and selective metal bumping processes during packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If interposers are used to connect integrated circuit dies, then interconnectivity between dies is achieved, but routing density and integration efficiency are limited
Solution Approach 1:
The patent extracts the interconnect function from the interposer substrate and integrates it directly onto the integrated circuit dies through edge interconnect features. By removing the interposer as a separate component and embedding the redistribution layer within the die structure itself, the routing density is dramatically improved while maintaining full interconnectivity functionality.
Solution Approach 2:
The patent transitions from planar interconnect routing on a separate interposer substrate to three-dimensional edge-based interconnect features that extend vertically from the die surface. This dimensional change allows multiple routing layers to be stacked vertically at the die edges, significantly increasing routing density without compromising adaptability.
2Reliability
If traditional bumping processes are used for die connection, then electrical connection is established, but manufacturing complexity and process steps are increased
Solution Approach 1:
The patent merges the electrical connection function with the interconnect structure itself by forming conductive lines that extend directly from the circuit region through the sealing ring to the edge of the die. This integration eliminates the need for separate bumping processes, reducing manufacturing complexity while maintaining reliable electrical connections through the edge interconnect features.
Solution Approach 2:
The edge interconnect features are formed during the semiconductor fabrication process before die separation, with conductive lines extending to the die edges and through sealing rings. This preliminary formation of interconnect structures eliminates the need for subsequent bumping operations, simplifying the manufacturing process while ensuring reliable electrical connections are already in place.
3Adaptability or versatility
If interposers are used for die interconnection, then signal routing is enabled, but power transfer efficiency is reduced
Solution Approach 1:
The patent extracts the power transfer path from the indirect route through the interposer substrate and creates direct power transfer pathways through the edge interconnect features. By removing the interposer from the power delivery path and establishing direct conductive connections between dies at their edges, power transfer efficiency is significantly improved while signal routing capabilities are maintained through the same edge interconnect structure.
Data Source
AI summary
Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and exposed on edge surfaces of the integrated circuit die. The edge interconnect features are configured to connect with other integrated circuit dies without going through an interposer. The semiconductor device may include two or more integrated circuit dies with edge interconnect features and connected through a RDL structure formed between the two or more integrated circuit dies.