Duty Cycle Corrector With Edge-Latching Inverter Timing Control
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Solution Overview
Problem
The manufacturing process distorts the duty cycle of internal clock signals in DRAM, leading to performance reduction and potential failure, as the ratio of high to low voltage levels differs from external clock signals, causing inaccuracies in clock generation.
Innovation Solution
A duty cycle corrector comprising a duty cycle detector and adjuster, utilizing partial edge-latching modulation (PELM) and complementary driving strength ratio correction (CDSRC) to generate control signals that adjust the output driving ability of an inverter, correcting system clock signals by delaying input changes and providing additional current paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the manufacturing process is scaled down to increase clock speed, then productivity is improved, but manufacturing precision deteriorates causing duty cycle distortion
Solution Approach 1:
The patent implements a feedback mechanism where the duty cycle detector continuously monitors the duty cycle of the clock signal and generates control signals to adjust the latch timing. This closed-loop feedback compensates for manufacturing variations and process distortions, maintaining accurate duty cycle despite scaled-down manufacturing processes that enable higher clock speeds.
Solution Approach 2:
The patent dynamically adjusts the latch timing parameter based on detected duty cycle deviations. By changing the latch timing parameter in response to measured distortions, the system compensates for manufacturing process variations without requiring changes to the physical manufacturing process itself, thereby maintaining productivity while improving precision.
2Reliability
If the duty cycle of internal clock signals is adjusted to match external clock signals, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent combines the duty cycle detection function and the latch timing adjustment function into an integrated clock generation circuit. Rather than adding separate complex correction circuits, the design merges these functions within the existing clock generation architecture, achieving reliability improvement while minimizing increases in device complexity.
Solution Approach 2:
The clock generation circuit performs self-correction by automatically detecting its own duty cycle deviations and adjusting its internal latch timing accordingly. This self-service mechanism eliminates the need for external complex correction circuits, maintaining simplicity while improving reliability.
3Manufacturing precision
If the latch timing is adjusted to correct duty cycle distortion, then manufacturing precision is improved, but forward path delay increases
Solution Approach 1:
The patent applies partial adjustment of the latch timing rather than full correction. By making incremental timing adjustments only when necessary to correct duty cycle deviations, the system achieves manufacturing precision improvement while minimizing the addition of forward path delay that would result from more aggressive correction mechanisms.
Data Source
AI summary
The duty cycle corrector for correcting a system clock signal comprises a duty cycle detector and a duty cycle adjuster. The duty cycle detector is configured for detecting a system duty cycle of the system clock signal and generating the first control signal and the second control signal, wherein the first control signal and the second control signal are complementary to each other. The duty cycle adjuster comprises an inverter and the duty cycle adjuster is configured for delaying a change in an input status of the inverter and adjusting of the inverter in accordance with the first control signal and the second control signal.