Edge Lighting LED Structure with Lateral Conducting Holes
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Solution Overview
Problem
Existing LED manufacturing methods face challenges in achieving high product yield, electrical performance, and alignment precision, particularly in edge lighting structures, where the contact area with external components is limited, affecting assembly efficiency and stability.
Innovation Solution
The design features a substrate with exposed conducting holes forming continuous junctions on its lateral surface, allowing for improved electrical connection and alignment with external components, along with a fluorescent layer and encapsulation layer to enhance light efficiency and structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional LED package structure is used with limited contact area, then the structure is simple, but the assembly efficiency and alignment precision with external components deteriorate
Solution Approach 1:
The patent transitions from a conventional top-contact configuration to a side-contact configuration where conducting holes are exposed on the lateral surface of the substrate. This dimensional change from vertical to lateral contact enables improved alignment precision and assembly efficiency with external components while maintaining structural simplicity
2Reliability
If the contact area with external components is increased, then the electrical performance and alignment precision improve, but the device complexity increases
Solution Approach 1:
The conducting holes are repositioned from the top surface to the lateral surface of the substrate, creating extended contact areas along the side walls. This lateral exposure of conducting holes provides larger contact areas for external components, improving electrical performance and alignment precision without significantly increasing overall structural complexity
Solution Approach 2:
The lateral surface of the substrate serves multiple functions: it provides mechanical support, exposes conducting holes for electrical connection, and enables alignment features for precise positioning with external components. This multi-functionality improves reliability without proportionally increasing complexity
3Manufacturing precision
If conducting holes are exposed on the lateral surface of the substrate, then the alignment precision and contact area improve, but the manufacturing complexity increases
Solution Approach 1:
The patent modifies the substrate structure to expose conducting holes on the lateral surface rather than the top surface. This dimensional reconfiguration enables improved alignment precision with external components while the manufacturing process remains compatible with conventional semiconductor fabrication techniques
Solution Approach 2:
The conducting holes are pre-formed and positioned within the substrate structure before final assembly with external components. This preliminary configuration of the electrode pattern and conducting holes enables precise alignment to be achieved during manufacturing, reducing the need for complex post-processing alignment operations
Data Source
AI summary
An edge lighting light emitting diode (LED) structure and a method of manufacturing the same are provided. The edge lighting LED structure includes a substrate, an electrode pattern, a chip, an encapsulation layer and a fluorescent layer. The electrode pattern at least includes two first conducting portions separately disposed on an upper surface of the substrate, two second conducting portions separately disposed on a lower surface of the substrate, and two conducting holes separately vertically penetrating through the substrate, each conducting hole connects a first conducting portion and a second conducting portion, and the conducting holes are exposed on a lateral surface of the substrate. A second surface of the chip is disposed on the first conducting portions. A top surface of the encapsulation layer exposes and is aligned with the first surface of the chip. The fluorescent layer covers a first surface of the chip.