Semiconductor Edge Metal Layout for Sawing Stress Isolation
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Solution Overview
Problem
Semiconductor devices face failures during manufacturing due to stress and impact issues, particularly during the sawing process, where metal structures on scribe lanes can be delaminated or cause bonding defects, leading to structural instability and increased failure rates.
Innovation Solution
A semiconductor device design featuring metal structures on the edge region of the substrate, spaced apart from the semiconductor components and surrounded by an insulating layer, which acts as a stress absorber and is not exposed during the sawing process, ensuring the semiconductor components remain protected and stable.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal structures are disposed on the scribe lane for test purposes, then test capability is improved, but structural stability deteriorates due to delamination and bonding defects during sawing
Solution Approach 1:
The patent divides the substrate into distinct regions: a device region containing semiconductor components and an edge region containing metal structures. This spatial segmentation isolates the metal structures to the edge region, preventing them from interfering with the semiconductor components while maintaining test capability. The insulating layer further segments the metal structures from the substrate, preventing direct contact that would cause delamination during sawing.
Solution Approach 2:
The patent introduces an insulating layer as an intermediary between the metal structures and the substrate. This insulating layer acts as a mediator that prevents direct bonding between the metal structures and the substrate, thereby eliminating bonding defects and delamination issues during the sawing process while still allowing the metal structures to serve their test function.
2Ease of operation
If metal structures are exposed at the side surface for accessibility, then ease of operation is improved, but structural stability worsens due to stress concentration and delamination
Solution Approach 1:
The patent extracts the metal structures from the main device region and places them exclusively in the edge region. This extraction removes the potentially harmful metal structures from the area where they could cause stress concentration and delamination, while they remain accessible in the edge region for testing purposes. The insulating layer further extracts the metal structures from direct contact with the substrate.
Solution Approach 2:
The insulating layer acts as a protective thin film that covers and isolates the metal structures. This thin film provides mechanical protection and stress distribution, preventing stress concentration at the metal structure-substrate interface while maintaining accessibility to the metal structures for testing through the insulating layer.
3Stability of the object's composition
If the insulating layer completely covers the metal structures, then structural stability is improved by preventing delamination, but manufacturing complexity increases
Solution Approach 1:
The patent applies the insulating layer selectively in the edge region where metal structures are located, rather than uniformly across the entire substrate. This local application of the insulating layer provides the necessary protection against delamination where metal structures exist, while minimizing the overall manufacturing complexity by limiting the insulating layer's coverage to only where it is needed.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate including a device region and an edge region; a semiconductor component on the device region; a metal structure on the edge region; an insulating layer surrounding the semiconductor component and the metal structure; and a pad on the semiconductor component, wherein the metal structure is surrounded by the insulating layer and is not exposed at a side surface of the insulating layer, and wherein the metal structure is electrically insulated from the semiconductor component.