Edge Placement Error Correction in Semiconductor Interconnect Fabrication
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Solution Overview
Problem
Edge placement errors during the fabrication of semiconductor devices in the back end of line (BEOL) process lead to defects such as unwanted vias and shorts, which are difficult to mitigate as critical dimensions scale down, limiting the margins for error.
Innovation Solution
A method is introduced to correct edge placement errors before patterning the underlying substrate, involving the use of a grating with alternating dielectric lines, a resist layer, and a conformal mask layer to fill and etch error openings, allowing for larger misalignment corrections and enabling smaller critical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gratings are used to provide increased overlay margins to avoid edge placement errors, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by performing a correction etch step before the final via formation. The method identifies edge placement errors in the grating pattern and removes affected portions through a controlled etch process, thereby correcting alignment issues before they propagate to subsequent layers. This preliminary correction enables larger overlay margins without requiring complex grating structures throughout the entire fabrication process.
2Productivity
If critical dimensions are scaled down to increase device density, then productivity is improved, but manufacturing precision deteriorates
Solution Approach 1:
The patent employs parameter changes by modifying the etch process parameters to selectively remove material based on edge placement errors. The correction etch uses specific etch selectivity ratios and duration parameters that allow removal of misplaced grating material while preserving correctly positioned features. This enables smaller critical dimensions to be manufactured with adequate error margins by dynamically adjusting process parameters rather than relying solely on fixed grating geometries.
3Device complexity
If edge placement errors are not corrected, then device complexity is reduced, but reliability deteriorates due to unwanted vias and shorts
Solution Approach 1:
The patent converts the harmful effect of edge placement errors into a beneficial correction mechanism. By intentionally designing the correction etch process to target and remove material at grating edges, the method transforms potential defect sources (misaligned via openings) into controlled features. The edge placement errors are not merely prevented but actively corrected by using the erroneous regions as targets for selective material removal, thereby improving reliability without adding complex inspection and rework processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates edge placement errors, increasing the margin for error and enabling the fabrication of semiconductor devices with smaller critical dimensions by accurately forming conductive vias and insulative plugs, reducing defects and improving device reliability.
Implementation Method 1
a conformal mask layer to fill and etch error openings
Implementation Method 2
a conformal mask layer to fill and etch error openings
Data Source
AI summary
Embodiments disclosed herein include edge placement error mitigation processes and structures fabricated with such processes. In an embodiment, a method of fabricating an interconnect layer over a semiconductor die comprises forming a patterned layer over a substrate, disposing a resist layer over the patterned layer and patterning the resist layer to expose portions of the patterned layer. In an embodiment, overlay misalignment during the patterning results in the formation of edge placement error openings. In an embodiment, the method further comprises correcting the edge placement error openings, and patterning an opening into the substrate after correcting edge placement error openings.