Edge-Slip Clock Generation for N.5 Modulus Division
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Solution Overview
Problem
Existing modulus counters are limited to integer divide ratios, resulting in high spurs and large voltage swings, and lack the flexibility to divide by non-integer values like N.5, which is necessary for more precise fractional-N PLL operations.
Innovation Solution
An edge-slip circuit is introduced that accepts a modulus count and a divisor select signal, using an XOR operation with a buffered clock signal to generate an output clock signal with skipped edges, effectively achieving a divide by N.5 ratio without altering other parameters, allowing for more flexible and reduced spur amplitude.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a modulus counter is limited to integer divide ratios, then the device complexity is reduced, but the adaptability and manufacturing precision deteriorate due to high spurs and large voltage swings
Solution Approach 1:
The modulus counter is transformed from a static integer divider to a dynamic divider that can switch between integer N and fractional N.5 ratios. The edge-slip circuit dynamically adjusts the divide ratio by selectively skipping clock edges based on a fractional indicator signal, enabling the counter to adapt between different division modes without requiring separate counter circuits for each ratio type.
Solution Approach 2:
An edge-slip circuit is introduced as an intermediary component between the clock signal source and the modulus counter. This circuit receives the clock signal, applies XOR operations with a fractional indicator signal to generate skipped edges, and feeds the modified clock signal to the counter. The intermediary handles the complexity of fractional division, allowing the main counter to remain relatively simple while achieving enhanced adaptability.
2Ease of manufacture
If a modulus counter uses integer divide ratios only, then the ease of manufacture is improved, but the measurement precision deteriorates due to high spurs in the output signal
Solution Approach 1:
The edge-slip circuit applies periodic skipping of clock edges based on the fractional indicator signal. When N.5 division is required, the circuit systematically skips every other clock edge, creating a controlled periodic pattern of edge omission. This periodic action transforms the integer divide ratio into an effective fractional divide ratio, improving frequency synthesis accuracy by reducing spurs while maintaining a relatively simple circuit implementation.
3Speed
If the clock signal frequency is increased to improve timing resolution, then the speed is improved, but the object-generated harmful factors worsen due to increased spurs and voltage swings
Solution Approach 1:
The invention converts the harmful effect of high-frequency clock edges into a beneficial feature by selectively skipping edges. The edge-slip circuit uses the high-frequency clock signal and, through XOR operations with the fractional indicator, transforms it into a controlled sequence with skipped edges. This converts the potential harm of high-frequency spurs into a benefit by using the same high-frequency signal to achieve precise fractional division with reduced spur amplitude through the skipping mechanism.
Data Source
AI summary
A system is provided for generating an output clock used for N.5 modulus division. An edge-slip circuit accepts a modulus count, a divisor select signal, and a clock signal having a frequency greater than a modulus count frequency. The edge-slip circuit also has an input to accept an output clock signal, and an output to supply a clock slip signal (NE). An exclusive-or (XOR) has an input to accept a buffered clock signal (NF) and the clock slip signal (NE). The XOR has an output to supply the output clock signal. The output clock signal has a frequency equal to a buffered clock signal frequency, with no skipped clock edges, when the clock slip signal does not change logic levels. Alternatively, the output clock signal frequency is equal to the buffered clock signal frequency, with a skipped clock edge, when the clock slip signal changes logic levels.