Junction-Less Edge Termination Using Implant Damage in Drift Layers
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Solution Overview
Problem
The high cost and complexity of manufacturing power semiconductor devices, particularly those using silicon carbide, due to the need for high-temperature ion implantation and annealing processes, and the limitations of conventional edge termination methods that require PN junction formation.
Innovation Solution
Forming a junction-less edge termination region in power semiconductor devices by implanting electrically active ions into the drift layer to create crystal lattice damage, eliminating the need for high-temperature annealing and specialized equipment, and using implantation damage to distribute electric field crowding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature ion implantation and annealing processes are used to form edge termination regions, then effective breakdown voltage performance is achieved, but manufacturing cost and processing complexity increase significantly
Solution Approach 1:
The patent extracts and eliminates the high-temperature annealing step from the conventional edge termination process. By using implantation damage alone without subsequent high-temperature annealing, the process complexity is reduced while maintaining the electrical activation needed for effective edge termination and breakdown voltage performance.
Solution Approach 2:
The patent changes the processing parameters by reducing the maximum temperature required. Instead of requiring high-temperature annealing (typically above 1600°C for SiC), the process uses lower temperature implantation and forms the edge termination region through implantation damage alone, thereby reducing processing complexity and equipment requirements.
2Reliability
If high-temperature annealing is performed to achieve lattice recovery and electrical activation, then edge termination functionality is achieved, but manufacturing cost and equipment requirements increase
Solution Approach 1:
The patent removes the expensive high-temperature annealing step from the manufacturing process. By relying on implantation damage to provide both the edge termination structure and sufficient electrical activation, the need for costly high-temperature equipment is eliminated, reducing manufacturing costs while maintaining functionality.
Solution Approach 2:
The patent uses a simpler, lower-cost implantation process that does not require expensive high-temperature annealing equipment. The implantation damage itself serves the dual purpose of creating the edge termination structure and providing electrical activation, eliminating the need for costly specialized equipment.
3Reliability
If conventional PN junction edge termination is used, then voltage blocking is achieved, but processing time and manufacturing complexity increase
Solution Approach 1:
The patent merges the edge termination structure formation and electrical activation into a single ion implantation step. The implantation damage simultaneously creates the physical structure and provides the electrical activation needed for voltage blocking, eliminating separate processing steps and reducing overall processing time.
Solution Approach 2:
The ion implantation process performs the preliminary action of creating both the edge termination structure and electrical activation in one step. The implantation damage is formed during the implantation process itself, providing the necessary electrical properties without requiring subsequent high-temperature annealing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces manufacturing costs and processing time while maintaining effective breakdown voltage performance, applicable to various semiconductor materials including silicon carbide, zinc oxide, and gallium nitride, without the need for high-temperature annealing.
Implementation Method 1
The edge termination region includes a damage region in the drift layer that is formed by implantation of electrically active ions into the drift layer. The implantation of electrically active ions generates crystal lattice damage to the drift layer.
Implementation Method 2
using implantation damage to distribute electric field crowding
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a first conductivity type and a drift layer on the semiconductor substrate. The semiconductor device includes an active region and an edge termination region adjacent at least a portion of the active region. The edge termination region includes a damage region in the drift layer that is formed by implantation of electrically active ions into the drift layer. Related methods are also disclosed.