Edge-Triggered Flip-Flop Design for Reduced Power and Noise
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Solution Overview
Problem
Traditional flip-flop designs face challenges in noise immunity, design space, and power dissipation, particularly in space- and power-conscious applications like handheld devices, where they require more design space and consume excessive electrical energy.
Innovation Solution
The proposed solution involves a switch circuit that generates a narrow clock pulse to properly pass and latch a data signal, and a data storage circuit that temporarily stores data before passing it to a permanent latching mechanism, utilizing a combination of pass gates, delay circuits, and inverters to achieve edge-triggered flip-flop functionality with reduced design space and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional master/slave latch mechanism is used, then noise immunity is improved, but device complexity and design space increase
Solution Approach 1:
The patent merges the master and slave latch circuits into a single integrated flip-flop structure with shared control logic. The first and second pass gates are controlled by complementary clock signals derived from a single clock line, reducing the number of independent control circuits while maintaining the master-slave latching mechanism's noise immunity.
Solution Approach 2:
The flip-flop circuit performs multiple functions within a single device: edge-triggered data capture, temporary storage in the first latch circuit, and transfer to permanent storage in the second latch circuit. This multi-functionality reduces the need for separate circuits and reduces overall design space while maintaining reliability.
2Reliability
If traditional master/slave latch mechanism is used, then noise immunity is improved, but power consumption increases
Solution Approach 1:
The circuit uses periodic clock signals to control the pass gates and trigger data transfer only at specific moments (rising and falling edges). This periodic action reduces power consumption by keeping circuits in high-impedance states during non-trigger periods, while still providing the noise immunity of the master-slave mechanism during active transfer windows.
Solution Approach 2:
The pass gates dynamically switch between conductive and high-impedance states based on clock signal edges. This dynamic operation reduces static power consumption while maintaining the ability to transfer data reliably during active periods, thus improving the power-reliability tradeoff.
3Reliability
If short duration pulse signal is generated, then vulnerability time is reduced, but precision and repeatability requirements increase
Solution Approach 1:
The circuit prepares complementary clock signals in advance using buffer circuits and inverters, so that when the data needs to be transferred, the control signals are already ready. This preliminary preparation reduces the critical timing window while not requiring extremely precise manufacturing, as the signal preparation happens before the actual data transfer moment.
Data Source
AI summary
An edge triggered flip-flop circuit is disclosed with a clock signal, an input signal, a switch module using the clock signal for defining a data passing window, and a latch module for receiving the input signal during the data passing window.