Edge Word Line Programming for Quad-Level Memory Cells

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In non-volatile memory devices, programming certain memory cells can adversely affect data in neighboring cells, leading to data retention losses, necessitating improved methods to mitigate interference and enhance data retention.

Innovation Solution

A memory apparatus and method where memory cells connected to multiple word lines are programmed using different techniques, with a control means or controller instructing the use of a first programming technique on one word line and a second technique on others, to manage threshold voltage and reduce interference across the memory array.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If memory cells are programmed using a uniform programming technique across all word lines, then the programming process is simple and fast, but data retention losses occur due to interference between neighboring memory cells

Engineering Contradiction:
Improvedata retentionVSAvoidprogramming technique complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies different programming techniques to different word lines based on their specific characteristics and interference profiles. Edge word lines receive enhanced programming with additional verify steps and adjusted voltages compared to inner word lines, optimizing data retention for each location without uniformly complicating the entire programming process

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The memory array is segmented into different word line categories (edge word lines vs. inner word lines), each subjected to appropriate programming techniques. This segmentation allows targeted interference mitigation where needed while maintaining efficiency in regions with lower interference risks

Inventive Principle:
Principle #1Segmentation

2Productivity

If programming voltage is increased to improve programming speed, then programming efficiency increases, but interference between neighboring memory cells increases causing data retention losses

Engineering Contradiction:
Improveprogramming speedVSAvoidinterference between memory cells
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent dynamically adjusts programming parameters including voltage levels, pulse widths, and verify thresholds based on word line position and data state requirements. Edge word lines use modified voltage profiles with additional verify steps at intermediate thresholds, while inner word lines use standard higher-voltage programming to maintain speed

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The programming process uses periodic verify steps interspersed among programming pulses, particularly for edge word lines. This periodic verification allows detection and correction of interference-induced errors before they become permanent data retention losses, enabling use of higher programming voltages

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20240363167A1Full sequence program for edge word line quad-level memory cells
Publication Date: 2024.10.31 SANDISK TECHNOLOGIES LLC
  • US20240363167A1 patent drawing
  • US20240363167A1 patent drawing
  • US20240363167A1 patent drawing

AI summary

A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes and is configured to program the memory cells in a program operation. During the program operation, the control means programs the memory cells connected to at least one particular word line of the plurality of word lines using a first programming technique while programming the memory cells connected to plurality of word lines other than the at least one particular word line using a second programming technique different than the first programming technique.