Single Memory Device Emulating Multiple EDID Sub-arrays
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Solution Overview
Problem
Conventional display devices with multiple memory devices for storing extended display identification data (EDID) lead to complex circuit designs and potential abnormal signal transmission due to parasitic capacitance, resulting in functional failures.
Innovation Solution
A display device with a memory array comprising sub-arrays, an input/output logic circuit to determine identification data access, and a control logic circuit to read EDID from a target sub-array based on memory address information, simplifying circuit design and avoiding capacitive issues by using a single memory device to emulate multiple memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple memory devices are used to store different EDID data for different display modes, then the display device can support multiple native resolutions, but the circuit design becomes complicated and parasitic capacitance causes signal transmission errors
Solution Approach 1:
The patent merges multiple separate memory devices into a single memory device that stores multiple EDID data sets. The memory device includes a memory array with multiple sub-arrays, each storing different EDID data for different display modes. This consolidation reduces the number of external memory components and simplifies the overall circuit design while maintaining the capability to support multiple native resolutions through selective access to different sub-arrays.
Solution Approach 2:
The single memory device is designed to perform multiple functions by storing and providing different EDID data sets for various display modes. The memory array is organized into multiple sub-arrays that can be selectively accessed based on the required display mode, allowing one memory device to replace what would traditionally require multiple separate memory devices, thereby reducing circuit complexity while maintaining versatility.
2Reliability
If multiple memory devices are used to store different EDID data, then the display device can provide accurate display information for different resolutions, but parasitic capacitance between the circuit board and memory devices causes erroneous signal transmission
Solution Approach 1:
By consolidating multiple memory devices into a single memory device with multiple sub-arrays, the patent reduces the total number of connection interfaces between the circuit board and memory components. This reduction in interfaces directly decreases the parasitic capacitance effects that cause signal transmission errors, while the internal memory array structure maintains the ability to provide accurate display information for different resolutions through selective sub-array access.
3Adaptability or versatility
If multiple memory devices are used for storing EDID data, then different native resolutions can be accessed, but the circuit design and manufacturing cost increase
Solution Approach 1:
The patent combines the functionality of multiple memory devices into a single memory device with a memory array divided into multiple sub-arrays. Each sub-array stores EDID data for a specific display mode and native resolution. This approach reduces the bill of materials by eliminating the need for multiple separate memory device components, simplifies assembly processes, and reduces manufacturing costs while maintaining full access to different native resolutions through controller-directed sub-array selection.
Data Source
AI summary
A display device, an electronic system and a control method are disclosed. The display device includes a memory device. The memory device includes a memory array, an input/output logic circuit and a control logic circuit. The memory array includes a plurality of sub-arrays and each sub-array stores extended display identification data. The input/output logic circuit is configured to receive an identification data request from a host device and determine whether to perform an identification data access process according to the identification data request The control logic circuit is configured to read extended display identification data stored in a target sub-array of the plurality of sub-arrays of the memory array according to memory address information in response to determining to perform the identification data access process.