Editing NoC Topology on Chip Floorplan
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Solution Overview
Problem
Designing network-on-chip (NoC) topologies within complex chip floorplans is challenging due to the increasing number of cores and complexity of physical constraints, as conventional methods often neglect spatial distribution and physical constraints, leading to inefficiencies and design errors.
Innovation Solution
A method and system that represent and edit NoC topologies on a physical view of a chip, allowing for the placement of elements within physical constraints, automatic suggestion of locations, and calculation of metrics such as wire length and latency, while ensuring connections follow Manhattan routes and avoid blockages, enabling interactive editing and optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional methods are used to design NoC topology, then design simplicity is maintained, but spatial distribution and physical constraints are neglected leading to design errors
Solution Approach 1:
The patent merges the NoC topology design view with the physical floorplan view into a single integrated graphical interface. This allows designers to simultaneously consider both logical connectivity and physical constraints, eliminating the need to switch between separate tools or mental models, thus maintaining design simplicity while improving design accuracy.
Solution Approach 2:
The system introduces an intermediary layer that automatically calculates and displays routing paths, wire lengths, and timing metrics based on the overlaid NoC topology and floorplan. This intermediary computation layer handles the complex analysis of physical constraints, allowing designers to work intuitively while ensuring design accuracy through automatic verification.
2Device complexity
If NoC topology is designed without physical view, then design process is simpler, but spatial distribution of elements cannot be optimized
Solution Approach 1:
The patent adds the physical spatial dimension to the traditional logical NoC topology design by overlaying the floorplan view. This transforms the design from a purely logical abstraction to a two-dimensional spatial representation, enabling optimization of element placement and routing while maintaining manageable design process complexity through automated calculations.
3Adaptability or versatility
If manual editing of NoC topology is performed, then flexibility is maintained, but time consumption increases
Solution Approach 1:
The system provides real-time feedback by automatically calculating and displaying routing paths, wire lengths, area utilization, and timing metrics as designers edit the NoC topology on the floorplan. This immediate feedback allows designers to make informed decisions and quickly iterate on designs, maintaining flexibility while reducing time consumption through automated verification.
Solution Approach 2:
The system performs self-service by automatically computing routing paths and timing metrics based on the current NoC topology and floorplan configuration. This eliminates the need for manual calculation or separate simulation steps, allowing designers to focus on creative topology design while the system handles repetitive analytical tasks.
Data Source
AI summary
A NoC topology is represented on top of a physical view of a chip's floorplan. The NoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of switches within the floorplan is automatically computed. Locations can also be edited by a user. Statistical metrics are calculated, including wire length, switch area, NoC area, and maximum signal propagation delay for logic in each of multiple clock domains. Wire density can also be overlaid on chip's floorplan on the display. The NoC topology is represented by a data structure indicating connections between initiator and target endpoints with ordered lists of switches in between. The data structures are written and read from memory or a non-transient computer readable medium. The locations of endpoint and switches are also written out, as scripts for place & route tools.