Extended Drain MOSFETs With Dual Gate Oxide Thickness
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Solution Overview
Problem
Conventional extended drain MOSFETs face limitations in high-frequency switching due to high input capacitance, leading to significant gate switching loss and breakdown issues in fully depleted silicon on insulator structures, particularly at frequencies beyond 1 MHz, with maximum breakdown voltage limited to about 11V.
Innovation Solution
The implementation of a dual oxide thickness scheme in the gate structure of extended drain MOSFETs, with a thicker oxide portion adjacent to the drain side and a thinner oxide portion under the remaining gate structure, helps in sustaining high gate stack/drift electric fields and reducing input capacitance, thereby enhancing breakdown voltage and switching efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional extended drain MOSFET structure is used, then the device can operate as a high frequency switch, but the input capacitance becomes large due to large gate area and gate-drain overlap
Solution Approach 1:
The patent applies local quality by implementing a dual oxide thickness scheme where the gate oxide thickness varies spatially: a first thickness in the channel region and a second (thicker) thickness in the drain region. This local differentiation allows the gate to maintain proper electrical control over the channel while reducing the overlapping capacitance with the drain, thus lowering input capacitance without compromising switching speed.
2Reliability
If the gate area is increased to improve switching control, then the switching performance improves, but the gate-to-drain capacitance increases significantly
Solution Approach 1:
The patent implements local quality through spatially varying gate oxide thickness, with a thinner oxide under the channel portion of the gate for strong control and a thicker oxide under the drain portion for reduced capacitance. This resolves the contradiction by making different parts of the gate serve different functions.
Solution Approach 2:
The gate structure is segmented into regions with different oxide thicknesses, allowing the gate to be functionally divided: one segment for control (thin oxide) and another for capacitance reduction (thick oxide). This segmentation enables the gate area to be large for good control while minimizing the harmful overlap capacitance.
3Power
If the breakdown voltage is increased to handle higher power, then the power handling capability improves, but breakdown occurs at the gate stack/drift region interface in FDSOI structures
Solution Approach 1:
The patent applies local quality by positioning a thicker gate oxide specifically at the drain region where the electric field is highest and breakdown is most likely to occur. This local reinforcement of the gate oxide at the critical gate stack/drift region interface prevents breakdown, enabling higher breakdown voltages and improved power handling capability.
4Reliability
If a thicker gate oxide is used to prevent breakdown, then the breakdown voltage increases, but the gate control over the channel deteriorates
Solution Approach 1:
The patent resolves this contradiction through local quality by using a first (thinner) gate oxide thickness in the channel region to maintain strong gate control and a second (thicker) gate oxide thickness in the drain region to prevent breakdown. Each region receives the oxide thickness appropriate to its functional requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces gate switching loss and increases the breakdown voltage beyond 11V, enabling improved performance in high-frequency and high-power applications without the need for complex biasing schemes, while maintaining low leakage levels and improved short channel control.
Implementation Method 1
sustaining high gate stack/drift electric fields
Implementation Method 2
thicker oxide portion adjacent to a drain side of the gate structure
Implementation Method 3
gate-to-drain capacitance (CGD) is known to exist due to the overlap of the gate
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to extended drain MOSFET structures with a dual oxide thickness and methods of manufacture. The structure includes an extended drain metal oxide semiconductor transistor (EDMOS) comprising a gate structure with a dual oxide scheme.