EDMOS FET Drift Region Biasing for High Breakdown and Low Resistance
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Solution Overview
Problem
Conventional NEDMOS and LDMOS FETs face high resistance in the extended drift region, which adversely affects their ability to handle high drain voltages and reduces drain current.
Innovation Solution
Incorporating a secondary transistor with a differently-doped well and a variably-biased secondary gate structure over the drift region, allowing for adjustable resistance by biasing the gate structure above the threshold voltage of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If an extended drift region is used in NEDMOS or LDMOS FETs, then breakdown voltage is improved, but drift region resistance increases
Solution Approach 1:
The drift region is segmented into multiple regions with different doping concentrations. A first drift region has a first doping concentration optimized for high breakdown voltage, while a second drift region has a second doping concentration optimized for low resistance. This segmentation allows each region to perform its specialized function, resolving the contradiction between high breakdown voltage and low resistance.
Solution Approach 2:
Different portions of the drift region are assigned different doping concentrations based on their specific functional requirements. The first drift region (closer to the drain) uses higher doping for voltage handling, while the second drift region (closer to the body) uses lower doping for current conduction. This local quality optimization resolves the global contradiction by making each local region specialized.
2Reliability
If doping concentration in the drift region is increased, then resistance is reduced, but breakdown voltage decreases
Solution Approach 1:
The drift region is divided into segments with different doping concentrations. The first segment near the drain uses higher doping to reduce resistance and improve current flow, while the second segment extends toward the body with lower doping to maintain high breakdown voltage. This segmentation resolves the contradiction by spatially separating the conflicting requirements.
Solution Approach 2:
Each portion of the drift region is doped according to its local functional needs. The region closer to the drain contact benefits from higher doping for lower resistance, while the region extending toward the body maintains lower doping for higher breakdown voltage. This local optimization resolves the global trade-off.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the breakdown voltage and drain current while improving linearity and error-vector magnitude characteristics of the MOSFETs.
Implementation Method 1
a field-effect transistor, including a well region within the drift region configured to have a first resistance when biased by a first bias voltage and to have a second resistance when biased by a second bias voltage
Data Source
AI summary
MOSFET-based IC architectures that mitigate or eliminate the relatively high resistance of extended drift regions in EDMOS and LDMOS devices, resulting in MOSFETs that are reliable, capable of handling relatively high drain voltages, and provide high currents at relatively low drain voltages. Embodiments encompass EDMOS or LDMOS devices that include a secondary transistor comprising a differently-doped well located adjacent at least one drift region and between the drain and the body of the device, with a variably-biased secondary gate structure aligned over the differently doped well. Biasing the secondary gate structure to an OFF state causes the differently-doped well to exhibit high resistance, resulting in a high breakdown voltage for the device. Biasing the secondary gate structure to an ON state causes the differently-doped well to exhibit low resistance, resulting in a reduced drain resistance path that improves the linearity and the error-vector magnitude characteristics of the device.