EDMOS Gate Isolation Structure for Uniform Oxide Thickness
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Solution Overview
Problem
The process of manufacturing extend-drain metal oxide semiconductor (EDMOS) transistors is complicated due to the uneven thickness of the gate insulating layer, which complicates the level shifter circuit design.
Innovation Solution
The isolation structure is used as a portion of the gate insulating layer in the EDMOS transistor, with specific configurations to ensure uniform thickness and avoid short circuits, integrating the process with FinFET manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate insulating layer thickness is increased adjacent to the drain to withstand higher voltage, then the voltage withstand capability is improved, but the manufacturing process complexity increases due to uneven thickness requirements
Solution Approach 1:
The gate insulating layer is segmented into two distinct regions: a first gate insulating layer adjacent to the source and a second gate insulating layer adjacent to the drain. This segmentation allows each region to have optimized thickness for its specific function while simplifying the overall manufacturing process by using separate formation steps for each region.
Solution Approach 2:
Different thickness specifications are applied to different locations of the gate insulating layer. The second gate insulating layer adjacent to the drain has a greater thickness than the first gate insulating layer adjacent to the source, allowing each region to have the appropriate quality for its local requirements.
2Adaptability or versatility
If the gate insulating layer has uneven thickness to accommodate both low-voltage and high-voltage regions, then the functional requirements are met, but the manufacturing process becomes more complicated
Solution Approach 1:
The gate insulating layer is divided into multiple segments (first and second gate insulating layers) that can be formed using separate manufacturing steps. This segmentation enables each segment to be optimized independently while maintaining overall functional adaptability.
Solution Approach 2:
The solution moves from a single-layer gate insulating structure to a multi-layer structure with different thicknesses in different regions. This dimensional change in the gate insulating layer configuration allows simultaneous satisfaction of both low-voltage and high-voltage functional requirements.
Data Source
AI summary
Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, first and second isolation structures, first, second and third gates, first, second and third gate insulating layers, a drift region, and source/drain regions. The substrate in the first region includes fins. The first isolation structure surrounds the fins and exposes a part of each fin. The second isolation structure is disposed in the substrate in the second region. The first gate is disposed on the exposed portions of the fins. The second gate is disposed on the substrate in the second region and on a portion of the second isolation structure. The second gate insulating layer is disposed between the second gate and the substrate. The drift region is disposed in the substrate on a side of the second isolation structure away from the second gate, and extends below the second isolation structure.