ED-MOS Device Shallow Drain Implant Low On Resistance
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Solution Overview
Problem
Conventional extended drain metal oxide semiconductor (ED-MOS) transistors have high power-on resistance (RON) which is not effectively reduced without compromising the breakdown voltage, and there is a need for semiconductor devices with reduced size and increased breakdown voltage without affecting RON.
Innovation Solution
A semiconductor device design featuring a substrate with a doped shallow drain implant, a thin oxide layer, and a conductive layer separated by a thick/thin oxide layer, along with a high temperature oxide layer and specific dopant concentrations, which reduces the power-on resistance while maintaining or increasing the breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the concentration of dopant in the drift region is reduced or the length of the drift region is increased to increase breakdown voltage, then the breakdown voltage is improved, but the power-on resistance increases
Solution Approach 1:
The patent applies local quality by creating distinct dopant concentration zones within the drift region. A first dopant concentration is used in a first portion of the drift region, while a second, different dopant concentration is used in a second portion. This allows different regions to have optimized properties: one region optimized for breakdown voltage and another for reduced resistance, thereby resolving the contradiction between high breakdown voltage and low power-on resistance.
2Device complexity
If the size of power semiconductor devices is reduced, then the device complexity and manufacturing cost are improved, but the breakdown voltage capability is compromised
Solution Approach 1:
The patent employs parameter changes by systematically varying dopant concentrations across different regions of the drift region. By changing the dopant concentration parameter from a uniform value to a spatially varying profile (first concentration in first portion, second concentration in second portion), the device achieves high breakdown voltage in a compact structure. This parameter optimization allows reduced device size without compromising breakdown voltage capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces the power-on resistance of ED-MOS transistors while maintaining or enhancing the breakdown voltage, allowing for smaller semiconductor devices with improved performance.
Implementation Method 1
a conductive layer separated from the substrate in part by a thin oxide layer and in another part by a thick/thin oxide layer
Implementation Method 2
a doped shallow drain implant disposed in the well substantially across a drift region
Data Source
AI summary
A semiconductor device, in particular, an extended drain metal oxide semiconductor (ED-MOS) device, defined by a doped shallow drain implant in a drift region. For example, an extend drain n-channel metal oxide semiconductor (ED-NMOS) device is defined by an n doped shallow drain (NDD) implant in the drift region. The device is also characterized by conductive layer separated from a substrate in part by a thin oxide layer and in another part by a thick/thin oxide layer. A method of fabricating a semiconductor device, in particular an ED-NMOS device, having a doped shallow drain implant of a drift region is also provided. A method is also provided for fabricating conductive layer disposed in part across a thin oxide layer and in another part across a thick/thin oxide layer.