Embedded DisplayPort Sink Device Clock Recovery
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Solution Overview
Problem
Conventional embedded DisplayPort systems face challenges in continuously recovering a stream clock with the same frequency during panel self refresh mode, especially when the source device is turned off, due to frequency differences between chips and the limitations of internal and external oscillators, which complicates the display of static images and increases costs.
Innovation Solution
The system employs a sink device with a timing controller that stores and regenerates stream data using an internal oscillator's clock, allowing the sink device to recover the stream clock in the panel self refresh mode by counting the oscillator clock and dividing it, thereby maintaining the same frequency as before the self refresh mode, without the need for additional trimming circuits or expensive external oscillators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an internal or external oscillator is used to recover stream clock in PSR mode, then the sink device can continuously display static images, but frequency differences between chips cause the stream clock frequency to differ from the original frequency
Solution Approach 1:
The patent applies preliminary action by storing the relationship between link symbol clock and stream clock frequencies during the normal operating mode before entering PSR mode. The timing controller records the stream clock frequency that corresponds to each link symbol clock frequency (270 MHz or 162 MHz) so that when PSR mode is entered and the source device is turned off, the pre-stored frequency relationship can be used to accurately recover the stream clock frequency without requiring frequency trimming during PSR operation.
2Measurement precision
If frequency trimming circuits are added to reduce frequency differences, then stream clock frequency accuracy improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent avoids adding frequency trimming circuits by performing the frequency calibration action in advance during normal operation. The timing controller stores the correspondence between link symbol clock frequencies and stream clock frequencies before PSR mode is activated. This preliminary measurement and storage of frequency relationships eliminates the need for complex real-time frequency trimming circuits during PSR mode, reducing device complexity while maintaining frequency accuracy.
Solution Approach 2:
The patent uses copying by storing the frequency relationship data (first stream data and second stream data) in the timing controller's memory. Instead of using complex circuits to generate or trim frequencies in real-time during PSR mode, the system copies the pre-measured frequency relationship from normal operation mode and uses it to recover the stream clock frequency accurately during PSR mode, simplifying the overall circuit design.
3Measurement precision
If external oscillators are used to eliminate frequency differences, then stream clock frequency accuracy improves, but manufacturing cost increases
Solution Approach 1:
The patent eliminates the need for expensive external oscillators by performing preliminary frequency measurement and storage during normal operation. The timing controller records the actual stream clock frequency corresponding to each link symbol clock frequency before PSR mode is activated. This preliminary action allows the system to use the internally generated oscillator during PSR mode while still achieving accurate frequency recovery through the pre-stored frequency relationship, thereby avoiding the additional cost of external oscillators.
Solution Approach 2:
The patent replaces expensive external oscillators with a cost-effective approach using the internal oscillator combined with pre-stored frequency data. Instead of investing in expensive external oscillation components, the system uses the inexpensive internal oscillator and compensates for frequency variations by utilizing the pre-measured frequency relationships stored in memory, achieving the same frequency accuracy at a lower manufacturing cost.
Data Source
AI summary
Provided are an embedded DisplayPort (eDP) system and a method for controlling a panel self refresh mode. The eDP system enters a panel self refresh (PSR) mode when an image to display is static in a general mode, and a sink device recovers a stream clock for displaying a static image in the PSR mode.