Error Detection Path Switching Circuit for Low Latency TSN
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Solution Overview
Problem
Current Time Sensitive Networking (TSN) solutions in automotive applications face challenges in meeting low latency and safety requirements, particularly in systems with traditional SRAMs that are prone to bit errors under harsh conditions, leading to potential safety issues due to reboot times exceeding Fault Tolerance Time Interval (FTTI) specifications.
Innovation Solution
The implementation of an Error Detection & Path Switching (EDPS) circuit between the Network Interface Controller (NIC) and SRAMs, which checks for ECC errors and redirects SRAM reads to SPI flash for uncorrectable errors, ensuring data integrity and reducing reboot times by providing correct data for critical operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional SRAMs are used in TSN systems, then data storage is achieved, but bit errors occur under harsh conditions leading to safety issues
Solution Approach 1:
An Error Detection & Path Switching (EDPS) circuit is introduced as an intermediary component between the NIC and SRAMs. This circuit detects bit errors in real-time and switches the data path to alternative storage locations, preventing erroneous data from reaching the TSN system while maintaining normal operation.
Solution Approach 2:
The system implements preemptive error detection and path switching mechanisms before bit errors can cause hazardous events. The EDPS circuit continuously monitors SRAM data integrity and prepares alternative data paths in advance, ensuring that if errors occur, the system can immediately switch to clean data sources without compromising safety.
2Reliability
If reboot is performed after bit errors, then system recovery is achieved, but reboot time exceeds Fault Tolerance Time Interval (FTTI) specifications
Solution Approach 1:
The EDPS circuit acts as an intermediary that prevents system crashes by detecting and correcting bit errors before they propagate. By switching to alternative data paths or correcting errors in real-time, the circuit eliminates the need for time-consuming reboots and keeps the system continuously operational within FTTI requirements.
Solution Approach 2:
Instead of allowing the system to crash and require a full reboot, the EDPS circuit rapidly detects errors and switches to backup data paths in real-time, effectively skipping the reboot process entirely and maintaining continuous system operation within the required fault tolerance time interval.
3Reliability
If Error Detection & Path Switching (EDPS) circuit is implemented, then data integrity is improved, but device complexity increases
Solution Approach 1:
The EDPS circuit is designed as a dedicated intermediary component with specialized error detection and path switching logic. By concentrating error handling functionality in this separate unit, the main TSN system architecture remains relatively simple while gaining robust error handling capabilities through the specialized mediator circuit.
Data Source
AI summary
Methods and apparatus for low latency fail-operational Time Sensitive Networking. An apparatus includes an error detection and path switching (EDPS) circuit comprising circuitry to read data from volatile memory, detect whether read data is errant, the errant data including one or more uncorrectable errors, and send a message to access correct data corresponding to the errant data stored in a non-volatile memory device, the message identifying the correct data to be returned to the EDPS circuit. The apparatus receives the correct data and enables the correct data to be read by circuitry coupled to the EPDS circuit. The EDPS circuit includes Error Correction Code (ECC) logic to detect uncorrectable errors, detect the data has no ECC errors, and detect and correct single-bit errors to obtain corrected data. Data with no ECC errors and corrected data is immediately made available for reading by the circuitry coupled to the EPDS circuit.