eDRAM Cache ECC Logic for Low Power Idle States
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Solution Overview
Problem
Embedded DRAM caches in processors consume high power due to frequent refresh requirements, especially in low-power states, as they are susceptible to device variations and leakage currents, leading to increased power consumption and reduced availability.
Innovation Solution
Implementing a low-latency, low-cost multi-bit error-correcting code (BCH code) that compensates for high failure rates in eDRAM caches, allowing for a longer refresh period without significant performance penalty, by using quick ECC logic for minor errors and high-latency ECC logic for multi-bit corrections, and leveraging spatial locality to reduce ECC bit storage overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If eDRAM cache is used to increase density, then memory capacity is improved, but power consumption increases due to frequent refresh requirements
Solution Approach 1:
The patent changes the refresh period parameter from traditional short intervals to extended intervals (e.g., 1ms, 10ms, or longer) by implementing error detection and correction mechanisms. This allows the eDRAM cache to retain data for longer periods without refresh operations, significantly reducing power consumption while maintaining memory capacity.
Solution Approach 2:
The patent introduces error detection and correction codes as an intermediary mechanism between the eDRAM cache and the CPU. These codes detect and correct bit errors that occur during extended refresh periods, enabling the system to use longer refresh intervals without data corruption, thus reducing refresh frequency and power consumption.
2Use of energy by moving object
If refresh period is extended to reduce power consumption, then power consumption is improved, but data reliability deteriorates due to device variations and leakage currents
Solution Approach 1:
The patent applies error detection and correction codes in advance to cache lines before they are stored in eDRAM. This preliminary protection allows the system to extend refresh periods without risking data integrity, as any bit errors that occur during extended storage can be detected and corrected when the data is accessed.
Solution Approach 2:
The patent implements a feedback mechanism where error detection codes monitor cache line integrity during extended refresh periods. When errors are detected, correction codes automatically fix them, providing feedback that enables the system to maintain data reliability even with extended refresh intervals, thus allowing further power reduction.
3Reliability
If traditional ECC is used to ensure data integrity, then data reliability is improved, but access latency increases due to full decoding requirements
Solution Approach 1:
The patent implements partial ECC decoding by first checking only syndrome bits to detect errors, and only performing full correction decoding when errors are actually detected. This partial action approach reduces the average access latency for error-free data while maintaining data integrity protection, as most cache accesses do not require full ECC processing.
Solution Approach 2:
The patent segments the ECC processing into two stages: a fast syndrome check stage that quickly detects errors with minimal latency, and a slower correction stage that only processes data when errors are detected. This segmentation allows the system to maintain high data reliability while minimizing the impact on access latency for the majority of error-free operations.
Data Source
AI summary
A cache memory system uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. In an embodiment, error correction logic may include a first error correction logic to determine a number of errors in data that is stored in a cache line of a cache memory, and a second error correction logic to receive the data from the first error correction logic if the number of errors is determined to be greater than one and to perform error correction responsive to receipt of the data. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state. Other embodiments are described and claimed.