eDRAM Cache Refresh via Shared Pipeline Multiplexing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High performance computer systems using eDRAM in cache architecture face performance degradation due to periodic refreshes, which can interfere with cache operations when dedicated circuitry is required for refreshing.
Innovation Solution
Implementing a cache system with a memory refresh requestor and interpreter on a single chip, where refresh requests are sent over the same cache pipelines as data access requests, allowing for efficient and integrated memory refresh management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If eDRAM is used in cache architecture to increase capacity and density, then memory capacity and access speed are improved, but periodic refresh operations cause performance degradation
Solution Approach 1:
The patent merges the refresh operation with data access operations by sending refresh requests through the same cache pipeline used for data access. The refresh requestor generates refresh requests that are multiplexed with data access requests, and the request interpreter distinguishes between refresh and data access requests, allowing both operations to share the same pipeline resources and reducing dedicated circuitry requirements.
Solution Approach 2:
The cache pipeline is designed to handle multiple functions - both data access operations and refresh operations - through a single unified pipeline. The request interpreter provides multi-functionality by identifying and routing different types of requests (refresh vs. data access) through the same pipeline infrastructure, eliminating the need for separate dedicated refresh circuitry.
2Reliability
If dedicated circuitry is used for eDRAM refresh operations, then data integrity is maintained, but device complexity and performance degradation increase
Solution Approach 1:
The patent combines refresh circuitry with the existing cache controller and pipeline infrastructure. The refresh requestor, request interpreter, and pipeline sharing mechanisms eliminate the need for separate dedicated refresh circuitry, reducing device complexity while maintaining data integrity through proper refresh operation execution.
Solution Approach 2:
The cache controller and pipeline are designed to perform multiple functions - handling both data access requests and refresh requests through the same infrastructure. The request interpreter provides intelligent routing to distinguish between refresh and data access operations, allowing the same circuitry to serve multiple purposes without compromising reliability.
3Reliability
If refresh requests are sent over separate dedicated pipelines, then refresh operations are ensured, but interference with cache operations and performance degradation occur
Solution Approach 1:
The patent merges refresh requests with data access requests into a single shared pipeline. The refresh requestor generates refresh requests that are multiplexed with data access requests, and the request interpreter distinguishes between the two types, allowing both operations to share pipeline resources and reducing interference compared to separate dedicated pipelines.
Data Source
AI summary
A memory refresh requestor, a memory request interpreter, a cache memory, and a cache controller on a single chip. The cache controller configured to receive a memory access request, the memory access request for a memory address range in the cache memory, detect that the cache memory located at the memory address range is available, and send the memory access request to the memory request interpreter when the memory address range is available. The memory request interpreter configured to receive the memory access request from the cache controller, determine if the memory access request is a request to refresh a contents of the memory address range, and refresh data in the memory address range when the memory access request is a request to refresh memory.