eDRAM DLL Timing Control Under PVT Variations
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Solution Overview
Problem
Traditional embedded DRAMs face challenges in maintaining optimal timing control for internal signals due to variations in process, voltage, and temperature conditions, leading to reduced operation speed and inefficiency.
Innovation Solution
Incorporation of a delay-locked loop (DLL) circuit that generates control signals with precise delays relative to the clock signal, allowing the DRAM array to operate effectively across various conditions by adjusting signal timings proportionally to the clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional self timed delay chain is used to control critical signal timings, then the timing control is implemented, but the timing relationship does not match the eDRAM cell array requirements under PVT variations, requiring greater timing margins and reducing operation speed
Solution Approach 1:
The patent implements a delay-locked loop (DLL) circuit that uses feedback mechanisms to continuously adjust and lock the timing of control signals to match the actual performance characteristics of the eDRAM cell array under varying PVT conditions. This feedback-based timing adjustment ensures optimal timing relationships without requiring excessive timing margins, thereby maintaining high operation speed while ensuring reliable timing control across all specified PVT conditions.
2Reliability
If greater timing margins are designed into the eDRAM to ensure proper operation under all PVT conditions, then reliability is improved, but the eDRAM operation speed is slowed down
Solution Approach 1:
The patent employs dynamic timing adjustment through the delay-locked loop circuit that automatically adapts the timing of control signals based on actual PVT conditions. Instead of using fixed, conservative timing margins, the system dynamically optimizes timing parameters in real-time, allowing the eDRAM to operate at maximum speed while maintaining reliability. This dynamic approach enables the timing to be adjusted upward when conditions permit, thereby increasing data processing throughput without sacrificing operational reliability.
3Measurement precision
If mini-arrays are added outside the real array area for timing tracking, then timing control accuracy is improved by matching PVT variations, but the chip area increases significantly
Solution Approach 1:
The patent merges the timing tracking functionality directly into the existing eDRAM cell array structure by implementing the delay-locked loop circuit within the array area itself. This integration eliminates the need for separate mini-arrays outside the real array area, as the DLL uses the actual array cells to generate timing references. Consequently, the chip area is minimized while still achieving accurate timing measurement and control through the unified array structure.
Data Source
AI summary
The present invention discloses an embedded dynamic random access memory (eDRAM) comprising a clock signal, at least one delay-locked loop (DLL) circuit coupled to the clock signal and configured to generate a plurality of control signals each having a predetermined delay from the clock signal, and at least one DRAM array coupled to the plurality of control signals, wherein the DRAM array operates in a plurality of steps controlled by the plurality of control signals.