eDRAM Memory Cell Voltage-Based MAC Operation PVT Robustness
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Solution Overview
Problem
Existing eDRAM-based CIMs are vulnerable to PVT variations, have nonlinear characteristics, and require frequent refreshes, leading to reduced operation accuracy and efficiency, especially when performing MAC operations on multi-bit data.
Innovation Solution
A memory cell based on eDRAM with a weight storage circuit and MAC operation circuit that uses a coupling capacitor for accurate voltage manipulation, allowing for robust PVT variation resistance and linear characteristics without the need for additional compensation circuits, enabling longer weight retention time and reduced refresh frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If eDRAM is used for CIM architecture, then memory cell size is reduced and memory capacity is increased, but operation accuracy is reduced due to PVT variation vulnerability
Solution Approach 1:
The patent changes the operating parameter from current-based MAC operation to voltage-based MAC operation. By applying input voltage to the coupling node and using the stored weight voltage to control discharge, the system achieves PVT variation robustness while maintaining small eDRAM cell size. The voltage-based operation inherently compensates for PVT variations without requiring larger cells.
2Quantity of substance
If eDRAM is used for CIM architecture, then memory capacity is increased, but additional compensation circuits are required due to nonlinear characteristics
Solution Approach 1:
The patent extracts and eliminates the nonlinear characteristic problem by using voltage-based operation instead of current-based operation. The voltage-based MAC operation inherently provides linear characteristics, removing the need for additional compensation circuits while maintaining high memory capacity in the eDRAM architecture.
3Duration of action of stationary object
If refresh is performed frequently to maintain eDRAM data, then weight retention is improved, but MAC operation speed is reduced
Solution Approach 1:
The patent applies preliminary action by precharging the coupling node to the input voltage level before the MAC operation begins. This precharging ensures that the coupling node is ready to receive the weight voltage control signal immediately, enabling faster operation and reducing the need for frequent refreshes while maintaining weight retention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances MAC operation efficiency by maintaining accurate operation under PVT variations, eliminating the need for compensation circuits and reducing refresh frequency, thus improving energy efficiency and operation speed for MAC operations on multi-bit data.
Implementation Method 1
A memory cell based on eDRAM according to an embodiment of the present disclosure, conceived to achieve the objectives above, comprises a weight storage circuit configured, when a write word line is activated, to receive a weight voltage, according to a weight value to be stored through a write bit line, transmit it to a storage node, and store, and, when a read word line is activated, to drop a read voltage precharged to a read bit line, according to a voltage level of the storage node, to a voltage level of the read word line; and a MAC operation circuit configured, when a data enable line is activated, to transmit an input voltage according to a value of input data to a coupling node through a data input line to charge it, and, to discharge the coupling node according to a level of the weight voltage stored in the storage node so that the coupling node has a voltage corresponding to a product of the input data and the weight
Data Source
AI summary
A memory cell comprises: a weight storage circuit configured, when a write word line is activated, to receive a weight voltage, according to a weight value to be stored through a write bit line, and transmit the weight voltage to a storage node, and, when a read word line is activated, to drop a read voltage precharged, according to a voltage level of the storage node, to a voltage level of the read word line; and a MAC operation circuit configured, when a data enable line is activated, to transmit an input voltage according to a value of input data to a coupling node through a data input line, and, to discharge the coupling node according to a level of the weight voltage stored in the storage node, and, when the data enable line is reactivated, to transmit a voltage change of the coupling node to a multiply word line.