Heterogeneous Deep Trench Fill for eDRAM Moat Isolation
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Solution Overview
Problem
Current semiconductor technologies face challenges with moat isolation in eDRAM due to Reactive Ion Etching (RIE) lag, leading to deeper recess depths in moat isolation regions and increased risk of substrate shorts, as well as local recess depth variations caused by interfacial layers between metal liners and poly fill materials.
Innovation Solution
The method involves forming deep trenches for both DRAM arrays and moat isolation regions with different critical dimensions, lining them with a dielectric material, and filling them with metal, where the metal in the DRAM array is recessed deeper than in the moat region to mitigate RIE lag and reduce cross-talk, using a heterogeneous deep trench fill process that includes a Si material in the moat region to ensure proper isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a poly filled deep trench is followed by a poly recess process, then moat isolation can be formed, but RIE lag causes the moat isolation region to have a deeper recess depth which prevents proper isolation and causes substrate shorts
Solution Approach 1:
The patent applies local quality by using different fill materials (metal for DRAM array trenches, dielectric for moat isolation trenches) in different regions. This allows the metal in DRAM trenches to be recessed deeper without causing substrate shorts, while the dielectric in moat trenches maintains proper isolation depth, thus resolving the RIE lag problem that previously caused uniform over-recessing in all regions
Solution Approach 2:
The patent segments the trench fill process into two distinct pathways: metal filling for DRAM array trenches and dielectric filling for moat isolation trenches. This segmentation allows independent optimization of recess depths for each region, preventing the substrate short issue in DRAM areas while maintaining isolation effectiveness in moat regions
2Strength
If metal liner and poly fill are used in deep trenches, then structural integrity is improved, but interfacial layer causes local recess depth variation at the DRAM array
Solution Approach 1:
The patent changes the material parameter of the trench fill from poly to metal, which fundamentally alters the etching behavior. Metal materials exhibit different etch rates and interface properties compared to poly, eliminating the interfacial layer issues that caused local recess depth variation. This parameter change maintains structural integrity while improving recess depth uniformity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances moat isolation, reduces cross-talk, and achieves improved local recess depth uniformity by eliminating RIE lag and allowing for a shallower recess depth in the moat isolation structure, while maintaining full metal fill in the DRAM array for lower resistance and better depth control.
Implementation Method 1
In current technologies, a poly filled deep trench is followed by a poly recess process which cannot avoid Reactive Ion Etching (RIE) lag between a DRAM array and a moat isolation structure.
Data Source
AI summary
An array or moat isolation structure for eDRAM with heterogeneous deep trench fill and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method further includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method further includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method further includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method further includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region.