eDRAM Refresh Controller Bus Clocking Bandwidth
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Solution Overview
Problem
Embedded dynamic RAM (eDRAM) refresh operations consume on-chip bandwidth, causing back pressure on the data bus and limiting memory access bandwidth when integrated on a chip, due to the need for periodic memory cell refreshing.
Innovation Solution
A refresh controller is implemented to manage the refresh process by clocking the data bus at a higher rate than the standard rate, reserving specific clock cycles for refresh operations, and prioritizing data entries based on their timeout values to ensure efficient bus utilization and minimize bandwidth constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If eDRAM is embedded on the chip to improve memory access bandwidth and performance, then memory access speed is improved, but refresh operations consume on-chip bandwidth and cause back pressure on the data bus
Solution Approach 1:
The system dynamically adjusts the clock rate of the data bus based on operational requirements. The clocking mechanism transitions between different rates: a first clock rate during refresh operations and a second, higher clock rate during normal memory access operations. This dynamic adjustment allows the system to optimize performance for different operational modes, achieving high memory access bandwidth when needed while accommodating refresh operations without causing sustained back pressure.
Solution Approach 2:
The patent changes the temporal parameter of the data bus clock rate to resolve the bandwidth conflict. By varying the clock rate parameter between two distinct values depending on the operational phase (refresh vs. access), the system accommodates both refresh requirements and high-performance memory access without permanent bandwidth loss. This parameter change approach allows flexible resource allocation in the time domain.
2Productivity
If the data bus is clocked at a higher rate to accommodate both memory access and refresh operations, then bus utilization efficiency is improved, but the clocking complexity increases
Solution Approach 1:
The system employs periodic action by alternating between two clock rates in a structured manner. Refresh operations occur at specific periodic intervals using the first clock rate, while memory access operations utilize the second, higher clock rate. This periodic alternation provides a predictable and manageable pattern for the clocking control logic, reducing complexity compared to fully dynamic rate adjustment while still achieving high bus utilization efficiency through optimized timing.
Data Source
AI summary
One or more blocks of dynamic random access memory are embedded together with a processor and a data bus on an integrated circuit. The data bus has a bandwidth b for general operation including memory access, the block of dynamic random access memory further requiring data refresh at a refresh rate r. The block thus forms an eDRAM on the integrated circuit, typically an ASIC. A refresh controller embedded with the eDRAM may control refresh by clocking the data bus at a rate higher than the rate of the data bus to accommodate both the required memory access and the required data refresh.