eDRAM Refresh Pausing via Mirror Bank Transfer
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Solution Overview
Problem
Dynamic random access memory (DRAM) systems face reduced availability and increased refresh overhead due to the necessity of periodic refresh operations, which conflict with normal read and write operations, impacting memory bandwidth and requiring higher operating frequencies.
Innovation Solution
The implementation of primary and mirror memory banks with transfer registers and bank select logic allows for pausing refresh operations during data access requests, latching data, and subsequently writing it to the mirror bank, enabling asynchronous refresh cycles and minimizing conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If periodic refresh operations are performed in DRAM, then data integrity is maintained, but memory availability and bandwidth are reduced
Solution Approach 1:
The memory system is divided into primary and mirror banks, allowing refresh operations to be performed on one bank while data access operations occur on the other bank, thereby segmenting the conflict between refresh and data access
Solution Approach 2:
Transfer registers are introduced as intermediary components between the memory arrays and the data access path. These registers can hold data during refresh operations and facilitate data transfer without interfering with the refresh process, acting as a buffer that resolves the conflict between refresh and data access
2Productivity
If refresh operations are performed during data access, then memory bandwidth is improved, but data access conflicts with refresh cycles
Solution Approach 1:
The system dynamically switches between primary and mirror banks based on operation type. During data access, the active bank is used, and during refresh, the other bank is refreshed. This dynamic switching allows both data access and refresh to proceed without conflict
Solution Approach 2:
Data is copied between primary and mirror banks through transfer registers. The mirror bank serves as a copy of the primary bank, allowing one to be accessed for data operations while the other undergoes refresh operations without affecting data integrity
3Productivity
If higher operating frequencies are used, then memory availability is improved, but power consumption and system complexity increase
Solution Approach 1:
The dual-bank architecture with transfer registers enables continuous data access operations while refresh operations are performed in parallel on the other bank. This eliminates idle time during refresh cycles and maintains continuous useful action without requiring higher operating frequencies
Data Source
AI summary
A first data access request to a first row of a first memory array of the DRAM is received while a refresh operation in the first memory array is executing. The refresh operation is paused. The first data access request is executed, and simultaneously, the bits of the first row of the first memory array, including any updates indicated in the first data access request, are latched to a transfer register. The bits latched to the transfer register are written to a corresponding first row in a second memory array of the DRAM. A bank select logic is updated to indicate that subsequent data access requests to the first row in the first memory array will be executed from the second memory array. The refresh operation is then resumed.