Non-Planar eDRAM Access Transistor Leakage Reduction
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Solution Overview
Problem
Conventional approaches to reducing gate-induced drain leakage (GIDL) in fin-FET devices, such as junction grading and oxide thickness control, are ineffective for scaled gate dimensions, leading to degraded performance and increased parasitic series resistance in eDRAM access transistors.
Innovation Solution
A selective oxidation process is used to differentiate fin width under the channel of the transistor without impacting fin width at source/drain regions, allowing for a thicker gate dielectric for leakage reduction while maintaining wider fin widths at source/drain regions to minimize series resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a thicker gate dielectric is used to reduce GIDL leakage, then leakage is reduced, but parasitic series resistance increases due to narrower fin widths at source/drain regions
Solution Approach 1:
The patent applies selective oxidation only to the gate region of the fin, creating a localized narrow fin region under the gate while maintaining wider fin regions at the source and drain. This local differentiation allows the gate region to have thicker gate dielectric for reduced GIDL leakage, while the source/drain regions maintain wider fins to minimize parasitic series resistance, thus resolving the contradiction between leakage reduction and resistance management
2Object-generated harmful factors
If conventional approaches (junction grading, oxide thickness control) are used to reduce GIDL, then leakage reduction is attempted, but performance degrades and parasitic series resistance increases in scaled gate dimensions
Solution Approach 1:
Instead of applying uniform oxidation or junction grading across the entire fin structure, the patent uses selective oxidation confined to the gate region. This localized approach reduces GIDL leakage at the critical gate area without adversely affecting the source/drain regions, thereby maintaining device performance and drive current while achieving leakage reduction in scaled gate dimensions
Solution Approach 2:
The fin structure is segmented into distinct regions with different properties: a narrow fin region under the gate for leakage control and wider fin regions at source/drain for current drive. This segmentation allows independent optimization of each region, enabling effective GIDL reduction without compromising overall device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces GIDL leakage and parasitic series resistance, enhancing the performance of eDRAM access transistors by enabling precise control of GIDL and maintaining high drive current.
Implementation Method 1
A selective oxidation process is used to differentiate fin width under the channel of the transistor without impacting fin width at source/drain regions
Data Source
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AI summary
Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors for eDRAM are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate and including a narrow fin region disposed between two wide fin regions. A gate electrode stack is disposed conformal with the narrow fin region of the semiconductor fin, the gate electrode stack including a gate electrode disposed on a gate dielectric layer. The gate dielectric layer includes a lower layer and an upper layer, the lower layer composed of an oxide of the semiconductor fin. A pair of source/drain regions is included, each of the source/drain regions disposed in a corresponding one of the wide fin regions.