eDRAM Unit Cell Via Capacitance Using FinFET and High-k Dielectric
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Solution Overview
Problem
The semiconductor industry faces challenges in further improving MOSFET performance through scaling due to traditional limits, necessitating new methods for enhancing performance beyond miniaturization.
Innovation Solution
The development of an embedded dynamic random access memory (eDRAM) device using FinFETs with vertical field effect transistors (VTFETs) and via capacitance, which involves forming a FinFET device with a via cap, depositing a conductive liner, filling with an organic dielectric layer, and using high-k materials to create a capacitance structure that reduces area and eliminates the need for deep trench caps and back-end-of-line high-k MIM capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional MOSFET scaling is continued, then transistor density improves, but performance improvement becomes difficult due to scaling limits
Solution Approach 1:
The patent transitions from planar MOSFETs to FinFETs, adding a vertical dimension to the transistor structure. The fins extend vertically from the substrate, creating a three-dimensional structure that increases the effective channel area and improves transistor density without simply miniaturizing the planar dimensions. This dimensional change allows continued performance improvement despite traditional scaling limits.
2Reliability
If deep trench caps are used for capacitance, then capacitance is achieved, but area is consumed and wiring complexities increase
Solution Approach 1:
The patent merges the capacitance structure with the existing FinFET vertical structure. The via cap capacitance is formed using the same vertical space and material layers as the FinFET, combining two functions (transistor and capacitor) into a shared structure. This eliminates the need for separate deep trench caps, reducing area consumption and wiring complexity while maintaining required capacitance.
3Reliability
If back-end-of-line high-k MIM capacitance is used, then capacitance is achieved, but manufacturing complexity and mask requirements increase
Solution Approach 1:
The patent forms the via cap capacitance structure during the front-end processing steps, before the back-end-of-line processes. The conductive liner and dielectric layers are deposited and patterned alongside the FinFET structure formation, eliminating the need for separate back-end MIM capacitance formation processes and their associated mask steps.
4Area of stationary object
If FinFET with via cap is formed, then area is reduced and wiring is simplified, but manufacturing precision requirements increase
Solution Approach 1:
The via cap structure is formed using self-aligned processes where the conductive liner and dielectric layers automatically align with the FinFET structure through conformal deposition. The vertical sidewalls of the fins serve as natural alignment references, eliminating the need for separate alignment steps and reducing manufacturing precision requirements despite the integrated structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a smaller unit cell area, reduced defects and wiring complexities, simplified mask requirements, and improved capacitance, enabling efficient integration and reliable wiring for next-generation FIN CMOS technology.
Implementation Method 1
etching portions of the conductive liner and a portion of the ODL
Implementation Method 2
depositing a high-k material within the contact trench... so that a capacitance with two conducting materials is sandwiched by the high-k material
Implementation Method 3
depositing a conducting material over the high-k material
Data Source
AI summary
A method is presented for forming an embedded dynamic random access memory (eDRAM) device. The method includes forming a FinFET (fin field effect transistor) device having a plurality of fins over a substrate and forming a via cap adjacent the FinFET device by forming a contact trench extending into a bottom spacer, depositing a conductive liner within the contact trench, filling the contact trench with an organic dielectric layer (ODL), etching portions of the conductive liner and a portion of the ODL, and removing the ODL. The method further includes depositing a high-k material within the contact trench and depositing a conducting material over the high-k material.