Elmore Delay Time Resistance Model for 3D Transistor Structures
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Solution Overview
Problem
Current simulation tools for integrated circuits, particularly those modeling complex transistor structures like FinFet, GAA, and CFET, face inaccuracies due to their reliance on traditional 1D current flow resistance models, which are not suitable for 2D and 3D structures, leading to inadequate modeling of resistance and delay times.
Innovation Solution
A 2D/3D field solver based on Elmore Delay Time (EDT) is developed to generate accurate resistor values for gate, source, and drain terminals of transistors, using a 3D coordinate system to determine Elmore delay times and average delay times, and then calculating point-to-point resistance values, applicable to non-planar devices such as FinFet, GAA, and CFET, and integrated into existing CAD/EDA systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional 1D current flow resistance models are used, then the modeling approach is simple and computationally efficient, but the accuracy of resistance modeling is insufficient for 2D and 3D transistor structures
Solution Approach 1:
The patent transitions from traditional 1D current flow models to 2D and 3D Elmore delay time models that account for the spatial distribution of resistance and capacitance in complex transistor structures. By solving Laplace's equation in multiple dimensions, the model captures the actual current flow paths in FinFet, GAA, and CFET devices, significantly improving resistance modeling accuracy while accepting increased computational complexity.
Solution Approach 2:
The patent changes the fundamental parameters of the resistance model from simple 1D resistance values to distributed 2D/3D resistance and capacitance parameters. By using Elmore delay time calculations based on Laplace's equation with appropriate boundary conditions, the model transforms discrete resistance parameters into continuous spatial distributions that accurately represent complex transistor geometries.
2Measurement precision
If 2D/3D field solver based on Elmore Delay Time is used, then the resistance modeling accuracy is improved, but the computational complexity and processing time increase
Solution Approach 1:
The patent pre-calculates Elmore delay times for various transistor geometries and stores them in lookup tables or databases. During circuit simulation, instead of solving the full 2D/3D Laplace equation, the system retrieves pre-computed delay values based on the specific transistor dimensions and configuration, dramatically reducing computation time while maintaining accuracy.
Solution Approach 2:
The patent divides complex 3D transistor structures into smaller volumetric elements and calculates Elmore delay times for each segment independently. By segmenting the device into manageable units with defined boundary conditions, the computational problem becomes tractable and can be solved more efficiently than treating the entire structure as a single complex domain.
3Reliability
If traditional resistance models are used for complex transistor structures, then the ease of manufacture and integration is maintained, but the reliability of circuit simulation is compromised
Solution Approach 1:
The patent develops a universal Elmore delay time-based resistance model that can handle multiple transistor types (planar, FinFet, GAA, CFET) within a single framework. By using the same Laplace equation solver with appropriately adjusted boundary conditions and geometry parameters, the model provides consistent and reliable simulation results across different device architectures, improving simulation reliability without requiring separate models for each transistor type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides improved accuracy in resistance modeling and timing verification for integrated circuits, enabling more precise simulation and design of complex transistor structures by accounting for 2D and 3D topologies, enhancing the performance and efficiency of electronic design automation tools.
Implementation Method 1
the EDT is determined by solving a Laplace's equation with a Neumann boundary condition. The Laplace's equation is of a form t ELMORE = G -1C TOT
Data Source
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AI summary
We disclose an integrated circuit design tool for modeling resistance of a terminal of a transistor such as a gate, a source, a drain, and a via. A structure of the terminal is specified in a data structure in memory using a three-dimensional (3D) coordinate system. For each of a plurality of volume elements in the specified structure, an Elmore delay time (EDT) is determined. For those volume elements in the plurality of volume elements that are located on a surface of the gate terminal which faces the channel region, an average EDT (aEDT) is determined based on the EDT. Point-to-point resistance values of the terminal are generated as a function of the aEDT and a capacitance of the terminal.