EEG Acquisition Clock Synchronization via Frequency Division
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Solution Overview
Problem
The challenge of clock asynchronization and collaborative processing between data acquisition and processing units in neurophysiological signal acquisition systems, particularly when using analog front-end chips with a sampling rate of 250 Hz and main control chips with a sampling rate of 256 Hz or multiples thereof, leads to abnormal data acquisition and synchronization issues.
Innovation Solution
A device and method that includes a frequency division circuit to convert the sampling rate of an analog front-end chip from 250 Hz to 256 Hz by modifying the external clock input and using a frequency division circuit to synchronize the clock frequency with the main control chip, ensuring clock synchronization and enabling synchronous processing of multiple physiological signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the analog front-end chip uses a sampling rate of 250 Hz with external clock 2.048 MHz, then the EEG signal acquisition precision is improved, but the main control chip cannot perform synchronous data processing at 256 Hz or its multiples
Solution Approach 1:
The patent changes the external clock frequency parameter from the standard 2.048 MHz to 2.097 MHz. This parameter change allows the analog front-end chip to operate at a sampling rate that is an integer multiple of 256 Hz (specifically 256 Hz when using 2.097 MHz clock with appropriate division), enabling the main control chip to perform synchronous data processing at 256 Hz or its multiples without clock asynchronization issues.
2Productivity
If the sampling rate is forcibly set to 256 Hz for acquisition, then the main control chip can process data synchronously, but clock mismatch occurs between the analog front-end chip and main control unit
Solution Approach 1:
The patent changes the external clock frequency from 2.048 MHz to 2.097 MHz and introduces a frequency division circuit with division ratio N. This combination allows the system to maintain clock synchronization between the analog front-end chip and main control chip while achieving 256 Hz or its multiples sampling rate, eliminating clock mismatch issues.
Solution Approach 2:
The patent introduces a frequency division circuit as an intermediary component between the external clock and the analog front-end chip. This intermediary performs N-fold frequency division on the 2.097 MHz clock signal to generate the appropriate sampling clock, enabling the main control chip to operate at 256 Hz or its multiples while maintaining synchronization with the data acquisition system.
3Adaptability or versatility
If the external clock frequency is changed from 2.048 MHz to 2.097 MHz, then the sampling rate can be adjusted to 256 Hz or its multiples, but the default sampling rate of the analog front-end chip becomes incompatible
Solution Approach 1:
The patent introduces a frequency division circuit as an intermediary that performs N-fold frequency division on the 2.097 MHz external clock. This intermediary component simplifies the overall system configuration by allowing the use of a fixed external clock frequency (2.097 MHz) while providing flexible sampling rates (256 Hz or its multiples) through programmable frequency division, reducing the complexity of clock configuration.
Data Source
AI summary
Provided are a device and method for acquiring and processing an electroencephalogram signal. The device includes: an analog front-end processing circuit including an analog front-end chip configured to take a clock signal with the first clock frequency from an external clock as a clock input, acquire an EEG signal to obtain an analog EEG signal, convert the analog EEG signal into a digital EEG signal, and transmit the digital EEG signal to the control unit; a frequency division circuit connected to the external clock and configured to perform N-fold frequency division on a clock crystal oscillator of the external clock to obtain a clock signal with a target clock frequency; and a control unit configured to take the clock signal with the target clock frequency as a clock input, and perform data processing on the digital EEG signal from the analog front-end chip.