Page-Erasable EEPROM Block Erase Method
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Solution Overview
Problem
Existing methods for erasing EEPROM-type memory, which emulate Flash memory, require large additional circuits, result in high energy and time consumption, reduce memory lifespan, and increase data corruption risks due to sector transfers and limited erase cycles.
Innovation Solution
A method for erasing page-erasable EEPROM-type memory that involves selecting word lines corresponding to page addresses, triggering simultaneous erasing of all selected word lines with a high erase voltage, and using a word line decoder to manage page addresses, allowing for efficient erasure of multiple pages without sector transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If Flash memory is used to emulate EEPROM memory with RAM, then erase-granularity is reduced to word size, but device complexity increases due to large additional circuits and RAM
Solution Approach 1:
The memory is divided into pages, each containing multiple words, allowing selective erasure of individual pages or groups of pages. This segmentation enables fine-grained control (word-level precision) without requiring complex emulation circuits, as the physical structure itself provides the necessary granularity.
Solution Approach 2:
Instead of using complex RAM-based emulation circuits to achieve word-level erasure in Flash memory, the patent uses a simplified page-erasable EEPROM structure where pages are copied or selected for erasure. This eliminates the need for large additional circuits while maintaining precise erase control.
2Ease of operation
If sector erasing is used in Flash memory, then erase operation is simplified, but energy consumption and time increase due to erasing entire sectors
Solution Approach 1:
The patent enables partial erasure of only the specific pages or words that need to be modified, rather than erasing entire sectors. This partial action approach reduces energy consumption and time while maintaining operational simplicity, as the user still specifies target addresses but only the necessary portions are erased.
Solution Approach 2:
Different regions of the memory can be treated differently: pages can be selectively erased based on their content and usage patterns. This local quality approach allows the system to erase only what is necessary, optimizing energy efficiency while maintaining ease of use through address-based selection.
3Manufacturing precision
If sector transfers between Flash memory and RAM are performed, then word-level writing is enabled, but data corruption risk increases and service life decreases
Solution Approach 1:
The patent extracts the problematic sector transfer step from the writing process. By enabling direct word-level or page-level programming in the EEPROM without requiring transfer through an intermediate RAM buffer, the system eliminates the data corruption risks associated with multiple transfers while maintaining precise writing control.
Solution Approach 2:
The memory structure itself provides the capability for precise word-level or page-level programming directly, without requiring external RAM assistance. This self-service approach eliminates the reliability issues of sector transfers while maintaining high writing precision.
4Adaptability or versatility
If multiple erase and program cycles are performed, then flexibility in data storage is improved, but memory lifespan decreases due to limited cycle endurance
Solution Approach 1:
The patent enables partial erasure of only the specific pages or words that need to be modified, rather than repeatedly erasing entire sectors. This partial action approach reduces the total number of erase cycles required, thereby extending memory lifespan while maintaining data storage flexibility through selective addressing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces energy and time consumption, extends memory lifespan, and minimizes data corruption by enabling efficient erasure of multiple pages without affecting unmodified sectors, thus combining the advantages of EEPROM and Flash memory technologies.
Implementation Method 1
the latch supplying in an active state and upon receiving an erase-trigger signal, a high erase voltage to the gates of floating-gate transistors of all the memory cells of the word line
Data Source
AI summary
A method for erasing a page-erasable EEPROM-type memory includes: the memory receiving a command associated with a set of addresses of pages of the memory to be erased, each page comprising several memory cell groups each forming a word, for each address of the set of addresses, selecting a word line corresponding to a page of the memory, and triggering the simultaneous erasing of all the selected word lines.