EEPROM Buffer Memory for I2C Bus Write Optimization
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Solution Overview
Problem
EEPROMs connected to an I2C bus cannot receive data while they are programming others, leading to prolonged write operation durations, as they can only acknowledge data reception after programming is complete, which restricts bus usage and increases operation time.
Innovation Solution
Incorporating a buffer memory between the data reception register and the column decoder, allowing data to be received and stored in a page while another page is being programmed, and acknowledging data receipt during the programming process to enable continuous bus usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the EEPROM waits for programming completion before acknowledging data receipt, then data integrity is ensured, but the write operation duration increases and bus availability decreases
Solution Approach 1:
The patent implements a buffer memory that receives and stores data pages before programming completes. This preliminary action allows the EEPROM to acknowledge data receipt immediately upon reception, while the actual programming occurs in the background from the buffer, thus resolving the contradiction between ensuring data integrity and reducing write operation duration.
2Reliability
If the EEPROM holds the bus until programming is complete, then data accuracy is maintained, but other peripherals cannot access the bus
Solution Approach 1:
The patent segments the data handling process into two independent stages: data reception and storage in buffer memory, and subsequent programming from the buffer. This segmentation allows the EEPROM to acknowledge data receipt and release the bus immediately, while programming continues independently, thus maintaining data accuracy while improving bus availability for other peripherals.
3Device complexity
If no buffer memory is used, then the device structure remains simple, but data writing speed is limited by programming duration
Solution Approach 1:
The patent introduces a buffer memory as an intermediary component between the data reception register and the column decoder. This buffer acts as a mediator that decouples the data reception process from the programming process, allowing continuous high-speed data reception while programming occurs at the slower EEPROM speed, thus significantly improving data writing speed with minimal additional complexity.
Data Source
AI summary
An EEPROM circuit includes a data reception register and a column decoder. A buffer memory having a size corresponding to the size of a data page is included between the data reception register and the column decoder.