EEPROM Memory Device Byte-Level Inhibit Potential
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Solution Overview
Problem
EEPROM memories face reduced life expectancy and data retention due to the grouping of multiple bytes per memory word, which necessitates re-writing of non-selected bytes during write operations, leading to increased stress and potential data corruption.
Innovation Solution
Implementing a memory device with a matrix memory plane where write operations include an erase cycle with an inhibit potential for non-selected bytes, preventing their erasure and reducing the stress on memory cells, thereby maintaining the original data and extending life expectancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple bytes are grouped per memory word to reduce control gate switching circuit surface area, then device area is reduced, but life expectancy is degraded due to necessary re-writing of non-selected bytes
Solution Approach 1:
The patent segments the memory word into multiple independent bytes, each with its own select line. This allows individual byte selection during write operations, so that only the targeted byte is erased and rewritten while other bytes remain unchanged. This segmentation enables the physical grouping of bytes in a memory word without forcing logical rewriting of all bytes, thus maintaining life expectancy while benefiting from area reduction.
Solution Approach 2:
The patent applies preliminary action by pre-configuring the erase inhibit potential on non-selected bytes before the erase cycle begins. This prevents the harmful erasure effect from affecting non-targeted bytes in advance, avoiding unnecessary rewriting operations and preserving memory cell integrity. The inhibit potential is established as part of the write operation setup, ensuring that only selected bytes undergo erasure.
2Area of stationary object
If multiple bytes are grouped per memory word to reduce control gate switching circuit surface area, then device area is reduced, but data retention is degraded due to potential data corruption during write operations
Solution Approach 1:
By segmenting the memory word into independently selectable bytes with individual select lines, the patent ensures that write operations affect only the targeted byte. Non-selected bytes are protected by the erase inhibit potential mechanism, preventing accidental erasure and data corruption. This segmentation approach maintains data integrity while allowing physical byte grouping for area efficiency.
Solution Approach 2:
The patent converts the potential harm of collective erasure into a benefit by using the erase inhibit potential mechanism. What would traditionally be a harmful side effect (erasing non-selected bytes) is transformed into a controlled feature where the inhibit potential actively protects non-targeted bytes. This converts a reliability problem into a solution that enhances data retention while maintaining area reduction benefits.
3Area of stationary object
If several bytes are grouped in a memory word, then surface area is reduced, but the acceleration factor for stress increases by N, dividing the lifetime by N
Solution Approach 1:
The patent segments the write operation into byte-level granularity by providing individual select lines for each byte within a memory word. This segmentation allows the system to perform write operations on a single byte basis rather than forcing rewriting of all N bytes in a word. Consequently, the stress acceleration factor is reduced from N to 1, preserving the full lifetime of memory cells while maintaining the area reduction benefits of byte-grouping architecture.
Solution Approach 2:
The patent changes the operational parameter of write granularity from word-level (affecting all N bytes) to byte-level (affecting 1 byte). This parameter change is achieved through individual byte select lines and the erase inhibit potential mechanism. By changing the effective write granularity parameter, the patent reduces the stress per operation from N-fold to single-byte stress, thereby preserving lifetime while maintaining compact architecture.
Data Source
AI summary
The memory device of the electrically-erasable programmable read-only memory type comprises write circuitry designed to carry out a write operation in response to receiving a command for writing at least one selected byte in at least one selected memory word of the memory plane, the write operation comprising an erase cycle followed by a programming cycle, and configured for generating, during the erase cycle, an erase voltage in the memory cells of all the bytes of the at least one selected memory word, and an erase inhibit potential configured, with respect to the erase voltage, for preventing the erasing of the memory cells of the non-selected bytes of the at least one selected memory word, which are not the at least one selected byte.