EEPROM Cell Charge Loss Time Measurement
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Solution Overview
Problem
Existing time measurement circuits require continuous power supply and are not compatible with memory manufacturing processes, with limited measurable time ranges and prone to measurement drift due to electric stress on dielectric materials.
Innovation Solution
A dual-gate MOS transistor-based EEPROM cell with a specific insulating layer structure allows for controllable charge retention and time measurement without continuous power, using a floating node connected to dual-gate transistors for charge evaluation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a capacitive component with spacer leakage is used for time measurement, then the circuit can measure time without continuous power supply, but the measurable time range is limited by dielectric intervention possibilities
Solution Approach 1:
The patent changes the physical parameters of the insulating layer by creating a dual-portion structure with different insulation properties. The first portion maintains high insulation for charge retention, while the second portion provides controlled leakage for time measurement, enabling extended time ranges without continuous power.
Solution Approach 2:
The insulating layer is divided into two distinct portions with different local qualities: the first portion (above the floating gate) provides strong insulation for charge storage, while the second portion (above the channel) provides controlled leakage pathways. This local differentiation enables both long-term charge retention and measurable time ranges.
2Duration of action of stationary object
If a capacitive component is charged for time measurement, then time information can be retained without power, but electric stress on the dielectric causes measurement drift over time
Solution Approach 1:
The patent modifies the electrical parameters of the insulating layer by introducing a second portion with reduced insulation. This creates a controlled leakage current that prevents excessive charge buildup, thereby reducing electric stress on the dielectric and minimizing measurement drift while maintaining adequate charge retention.
Solution Approach 2:
The patent converts the harmful effect of complete charge retention (which causes dielectric stress and measurement drift) into a beneficial controlled leakage through the second insulating portion. This controlled leakage acts as a safety valve that prevents dielectric breakdown while maintaining time measurement capability.
3Use of energy by moving object
If a specific capacitive component structure is formed for time measurement, then time measurement without power is achieved, but the structure is incompatible with memory manufacturing steps
Solution Approach 1:
The dual-gate transistor structure with the modified insulating layer serves multiple functions: it acts as both a memory cell (storing charge on the floating gate) and a time measurement device (through the controlled leakage via the second insulating portion). This multi-functionality makes it compatible with existing memory manufacturing processes while enabling time measurement capability.
Solution Approach 2:
The patent merges the time measurement function with the memory cell structure by integrating the dual-portion insulating layer into the dual-gate transistor. The same physical structure that stores data (floating gate charge) also enables time measurement through controlled leakage, eliminating the need for separate components and manufacturing steps.
4Measurement precision
If residual charge in a capacitive component is measured for time determination, then time information is obtained, but calibration steps are required to generate charge-to-time conversion tables
Solution Approach 1:
The dual-gate transistor structure inherently provides a controlled leakage pathway through the second insulating portion that creates a predictable relationship between charge loss and time. This self-regulating mechanism reduces the need for external calibration, as the leakage rate is determined by the physical structure rather than requiring empirical calibration tables.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate time measurement even when the circuit is not powered, with extended time ranges and reduced measurement drift, and is compatible with memory cell technologies.
Implementation Method 1
an insulating layer being formed of a first portion and of a second portion less insulating than the first portion
Implementation Method 2
the second portion being located, at least partly, above a channel region of the transistor
Implementation Method 3
information representative of the time elapsed between two events... measuring the charge of a capacitive component
Implementation Method 4
a dual-gate MOS transistor having its two gates separated by an insulating layer
Data Source
AI summary
An EEPROM memory cell includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer. The insulation layer includes a first portion and a second portion having lower insulation properties than the first one. The second portion is located at least partially above a channel region of the transistor.