EEPROM Cell Refresh Circuit for Erase Granularity and Footprint
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Solution Overview
Problem
Existing EEPROM memories face challenges with high erase-granularity, limited service life, and increased footprint due to the need for cumbersome RAM circuits and excessive erase and programming cycles, which reduce the durability and miniaturization of memory cells.
Innovation Solution
A method for writing in EEPROM memory that involves specific read modes and voltage applications to selectively erase and program memory cells, reducing the number of cycles and minimizing the size of memory cells, while maintaining the integrity of programmed and erased states, thereby extending the service life and reducing the footprint of the memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a RAM memory is implemented to store sector data and emulate EEPROM with fine erase-granularity, then the erase-granularity is improved, but the device complexity and footprint increase due to additional RAM circuits
Solution Approach 1:
The patent extracts the RAM emulation function and replaces it with a dedicated refresh circuit that performs selective refresh operations on memory cells. This eliminates the need for separate RAM circuits while maintaining fine erase-granularity capability through targeted cell refresh during write operations.
Solution Approach 2:
The memory cell array is designed to serve multiple functions: it acts as both the EEPROM storage medium and the refresh target. The same memory cells used for data storage are also refreshed selectively during write operations, eliminating the need for separate RAM structures and reducing overall device complexity.
2Duration of action of stationary object
If selective refresh of memory cells is performed during write operations, then the service life is improved by reducing erase cycles, but the write operation complexity increases
Solution Approach 1:
The patent merges the refresh operation with the write operation by performing selective cell refresh during the write process. The refresh circuit uses the same control signals and timing as the write operation to identify and refresh only the cells that will be overwritten, combining two functions into one unified process.
Solution Approach 2:
The refresh operation is performed preliminarily during the write cycle before the actual programming occurs. By refreshing the cells that will be overwritten during the write operation itself, the patent ensures these cells are prepared for new data while avoiding unnecessary erase cycles on cells that will retain their current values.
3Area of moving object
If transistor size is decreased to miniaturize memory cells, then the footprint is reduced, but the control voltages must be increased which risks partial programming or erasing
Solution Approach 1:
The patent applies different control strategies to different groups of memory cells based on their state. Refresh operations are selectively applied only to cells that need them (those that will be overwritten), while cells maintaining their current state receive different treatment. This localized approach allows miniaturization while maintaining precise control over programming and erasing operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method allows for efficient writing operations with reduced erase and program cycles, minimizing the impact on memory cells and enabling the miniaturization of memory cells, thus enhancing the service life and reducing the footprint of EEPROM memories.
Implementation Method 1
Such a memory cell functions based on the tunnel effect (or Fowler-Nordheim effect) which involves inducing displacements of the threshold voltage of the floating-gate transistor by injecting or withdrawing charges from the floating gate through a thin oxide layer separating the floating gate from a doped region.
Data Source
AI summary
The present disclosure relates to a method for writing in an EEPROM memory, the method comprising steps of: storing the bits of a word to be written in first memory units, erasing a word to be modified, formed by first memory cells connected to a word line and first bit lines, reading bits stored in the memory cells of a word line WL, in a first read mode and storing the bits read in second memory units, reading in a second read mode the bits stored in the memory cells of the word line, and programming each memory cell of the word line connected to a memory unit storing a bit in the programmed state of the word to be written, of an erased word or of a word comprising a bit having different states in the first and second read modes.