EEPROM Core Structure Embedded in BCD Process
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Solution Overview
Problem
The complexity of integrating EEPROM into BCD processes and the traditional EEPROM core structure formation makes the process unsuitable for industrial applications due to the high number of photolithography layers required.
Innovation Solution
An EEPROM core structure is embedded into the BCD process using an LDNMOS transistor as the selection transistor, with a floating gate of the storage transistor having a hollow box-shaped plane figure, and a tunnel ion implanting process is added to form a tunnel injection layer, significantly reducing the complexity of the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional EEPROM core structure is embedded into BCD process, then EEPROM functionality is achieved, but process complexity becomes too high with more than 23 photolithography layers
Solution Approach 1:
The patent merges the EEPROM core structure formation with the BCD process by using the same photolithography layers and processing steps for both EEPROM and BCD devices. The EEPROM bit cell is integrated into the BCD process flow, sharing common layers such as the first conductive layer, second conductive layer, and insulating layers, thereby achieving EEPROM functionality without adding excessive process complexity
Solution Approach 2:
The patent creates a multi-functional process where the same photolithography layers and processing steps serve dual purposes: forming both BCD devices (bipolar transistors, CMOS transistors, resistors, capacitors) and EEPROM core structures. The first conductive layer, second conductive layer, and various insulating layers are used universally for both BCD and EEPROM components, making the process highly efficient
2Reliability
If traditional EEPROM core structure with high voltage NMOS transistor is used, then storage functionality is achieved, but manufacturing complexity increases due to separate formation processes
Solution Approach 1:
The patent combines the formation of high voltage NMOS transistor and storage transistor into a single integrated process. The same photolithography layers (first conductive layer, second conductive layer) and processing steps are used to form both transistor types simultaneously within the EEPROM bit cell, eliminating the need for separate formation processes and reducing manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the EEPROM core structure formation by sharing most processing steps with the BCD process, reducing the overall complexity and making it feasible for industrial applications.
Implementation Method 1
a tunnel injection layer in the active area of the storage transistor
Data Source
AI summary
The present invention provides an EEPROM core structure embedded into BCD process and forming method thereof. The EEPROM core structure embedded into BCD process comprises a selection transistor and a storage transistor connected in series, wherein the selection transistor is an LDNMOS transistor. The present invention may embed the procedure for forming the EEPROM core structure into the BCD process, which is favorable to reduce the complexity of the process.