EEPROM Cell Pairing via Cross-Connected Bit Line Select Transistors
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Solution Overview
Problem
Conventional EEPROM memory architectures with two cells per bit require significant space and resources for simultaneous erasing and writing, as they need multiple control gate select transistors and ground lines, making them costly and inefficient.
Innovation Solution
A memory device design where each memory cell's bit line select transistor serves as the control gate select transistor for the other cell, eliminating the need for specific control gate select transistors and ground lines, allowing for a single programming cycle with two memory cells per bit, and using a symmetrical memory latch to control both bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional EEPROM memory architectures with two cells per bit are used, then data integrity is improved through redundancy, but device area and structural complexity increase due to requiring multiple control gate select transistors and ground lines
Solution Approach 1:
The patent merges the control gate select transistor of one memory cell with the bit line select transistor of another memory cell. Specifically, the control gate of the first memory cell is connected to the bit line select transistor of the second memory cell, and vice versa. This sharing of transistors reduces the total number of control gate select transistors from two to one per bit pair, thereby reducing device area while maintaining the two-cells-per-bit redundancy for data integrity
Solution Approach 2:
The bit line select transistor serves dual functionality: it acts as the bit line select transistor for its associated memory cell and simultaneously serves as the control gate select transistor for the other memory cell in the pair. This multi-functionality eliminates the need for separate control gate select transistors, reducing overall device complexity and area
2Reliability
If conventional EEPROM memory architectures with two cells per bit are used, then data integrity is improved through redundancy, but device complexity increases due to requiring multiple control gate select transistors and ground lines
Solution Approach 1:
The patent merges the control gate select transistor of one memory cell with the bit line select transistor of another memory cell. Specifically, the control gate of the first memory cell is connected to the bit line select transistor of the second memory cell, and vice versa. This sharing of transistors reduces the total number of control gate select transistors from two to one per bit pair, thereby reducing device area while maintaining the two-cells-per-bit redundancy for data integrity
Solution Approach 2:
The bit line select transistor serves dual functionality: it acts as the bit line select transistor for its associated memory cell and simultaneously serves as the control gate select transistor for the other memory cell in the pair. This multi-functionality eliminates the need for separate control gate select transistors, reducing overall device complexity and area
3Productivity
If individual control gate select transistors are provided for each memory cell to enable simultaneous erasing and writing, then programming speed is improved, but device area increases significantly
Solution Approach 1:
The patent merges the control gate select transistor of one memory cell with the bit line select transistor of another memory cell. Specifically, the control gate of the first memory cell is connected to the bit line select transistor of the second memory cell, and vice versa. This sharing of transistors reduces the total number of control gate select transistors from two to one per bit pair, thereby reducing device area while maintaining the two-cells-per-bit redundancy for data integrity
Solution Approach 2:
The bit line select transistor serves dual functionality: it acts as the bit line select transistor for its associated memory cell and simultaneously serves as the control gate select transistor for the other memory cell in the pair. This multi-functionality eliminates the need for separate control gate select transistors, reducing overall device complexity and area
4Productivity
If multiple control gate select transistors and ground lines are used for two cells per bit, then simultaneous erasing and writing capability is achieved, but manufacturing cost increases
Solution Approach 1:
The patent merges the control gate select transistor of one memory cell with the bit line select transistor of another memory cell. Specifically, the control gate of the first memory cell is connected to the bit line select transistor of the second memory cell, and vice versa. This sharing of transistors reduces the total number of control gate select transistors from two to one per bit pair, thereby reducing device area while maintaining the two-cells-per-bit redundancy for data integrity
Solution Approach 2:
The bit line select transistor serves dual functionality: it acts as the bit line select transistor for its associated memory cell and simultaneously serves as the control gate select transistor for the other memory cell in the pair. This multi-functionality eliminates the need for separate control gate select transistors, reducing overall device complexity and area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves space savings and simplifies decoding, enabling simultaneous erasing and writing of bits within a single programming cycle while reducing the overall area requirement and complexity of the memory device.
Implementation Method 1
The programming or erasing of a floating-gate transistor includes injecting electrical charges into the gate of a transistor, or extracting electrical charges therefrom, through the tunnel or Fowler-Nordheim effect
Implementation Method 2
The programming or erasing of a floating-gate transistor includes injecting electrical charges into the gate of a transistor, or extracting electrical charges therefrom, through the tunnel or Fowler-Nordheim effect
Data Source
AI summary
The memory device includes a memory cell unit of the electrically erasable and programmable non-volatile type including two memory cells respectively connected to two bit lines via two bit line select transistors. The common terminal between the bit line select transistor and the floating-gate transistor of each memory cell of the memory cell unit is connected to the control gate of the floating-gate transistor of the other memory cell of the memory cell unit.