EEPROM Programming via Drain Current Sensing
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Solution Overview
Problem
Conventional EEPROM memories require separate verify operations to ensure accurate programming, leading to inefficiencies such as longer programming cycle times and reduced memory density due to the need for program-and-verify cycles and data masking to avoid over-programming.
Innovation Solution
The implementation of a self-compensating programming method where the programming current is controlled by a current comparator that senses the drain current decay of the memory cell, allowing for direct termination of the programming pulse without additional verify steps, eliminating the need for data masking and reducing programming time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate verify operations are used to ensure accurate programming, then programming accuracy is improved, but programming cycle time increases
Solution Approach 1:
The patent merges the programming and verify operations into a single integrated process. The verify operation is performed concurrently with programming by sensing the drain current during the programming pulse application, eliminating the need for separate verify cycles and reducing overall programming time while maintaining accuracy
Solution Approach 2:
The patent maintains continuous programming action by implementing adaptive voltage control that adjusts the programming pulse voltage in real-time based on sensed drain current. This allows the programming process to continue without interruption or separate verify steps, as the system continuously monitors and adjusts to achieve the desired programmed state
2Manufacturing precision
If data masking is applied to avoid over-programming, then programming accuracy is improved, but device complexity increases
Solution Approach 1:
The patent implements feedback control by sensing the drain current during programming and using this information to adjust the programming pulse voltage. The control circuit monitors the current flow and dynamically modifies the applied voltage to achieve the desired threshold voltage shift, preventing over-programming without requiring complex data masking circuits
Solution Approach 2:
The memory cell itself provides the feedback signal through its drain current characteristics. The cell's own electrical response during programming is used to control the programming process, eliminating the need for external masking circuits or additional control logic to prevent over-programming
3Productivity
If programming current is increased to speed up programming, then programming speed is improved, but risk of over-programming increases
Solution Approach 1:
The patent employs dynamic voltage adjustment during the programming process. The programming pulse voltage is not fixed but is continuously adapted based on the real-time drain current response of the memory cell. This allows high initial currents for fast programming while dynamically reducing voltage to prevent over-programming as the cell approaches the target state
4Manufacturing precision
If program-and-verify cycles are used, then programming accuracy is improved, but memory density decreases
Solution Approach 1:
The patent combines multiple programming and verify cycles into a single integrated operation. By performing verify sensing concurrently with programming through drain current measurement, the system eliminates the sequential nature of traditional program-verify cycles, effectively doubling the useful work performed in each cycle and improving overall density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate and efficient programming of EEPROM cells without separate verify operations, reducing programming time and improving memory density by directly sensing the programmed state through drain current decay, thus preventing over-programming and ensuring tightly controlled threshold voltages.
Implementation Method 1
a first current comparator senses a drain current of the memory cell
Implementation Method 2
the tunneling mechanism may be Fowler-Nordheim tunneling or channel 'hot' carrier injection
Implementation Method 3
the tunneling mechanism may be Fowler-Nordheim tunneling or channel 'hot' carrier injection
Data Source
AI summary
An electrically programmable non-volatile memory array and associated circuitry, including programming circuitry that adaptively senses completed programming of a selected memory cell. A programming bit line driver is connected to the bit line, and a first transistor has its source/drain path connected in series with the memory cell, and its gate connected to the output of the current comparator. As the MOS transistor in the selected cell becomes programmed, its drain current drawn from the bit line driver decays, and a remainder current into the current comparator increases. Upon the remainder current exceeding the reference current, the comparator turns off the first transistor; a second transistor connected between the source and drain of the cell transistor is turned on. In another approach, a summed current controls the gates of the first and second transistors. Programming terminates, and over-programming is avoided.